drm/amdgpu: Flush TLB after mapping for VG20+XGMI

For VG20 + XGMI bridge, all mappings PTEs cache in TC, this may have
stall invalid PTEs in TC because one cache line has 8 pages. Need always
flush_tlb after updating mapping.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index f0aec04111a38bbb2e81697622178fb4d39450c5..383242952a20d719a05fef9bd2b83fe6c01ef95c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -837,6 +837,12 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
                goto error_unlock;
        }
 
+       /* Vega20+XGMI where PTEs get inadvertently cached in L2 texture cache,
+        * heavy-weight flush TLB unconditionally.
+        */
+       flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
+                    adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0);
+
        memset(&params, 0, sizeof(params));
        params.adev = adev;
        params.vm = vm;