net/mlx5: Add misc5 flow table match parameters
authorMuhammad Sammar <muhammads@nvidia.com>
Sun, 5 Sep 2021 12:16:21 +0000 (15:16 +0300)
committerSaeed Mahameed <saeedm@nvidia.com>
Fri, 31 Dec 2021 08:17:23 +0000 (00:17 -0800)
Add support for misc5 match parameter as per HW spec, this will allow
matching on tunnel_header fields.

Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/fs_core.h
include/linux/mlx5/device.h
include/linux/mlx5/mlx5_ifc.h
include/uapi/rdma/mlx5_user_ioctl_cmds.h

index 7711db245c6387b8bd40bcf18a00aa88993c05be..5469b08d635f11ec5f3116d88af5fa7f7b211b16 100644 (file)
@@ -203,7 +203,7 @@ struct mlx5_ft_underlay_qp {
        u32 qpn;
 };
 
-#define MLX5_FTE_MATCH_PARAM_RESERVED  reserved_at_c00
+#define MLX5_FTE_MATCH_PARAM_RESERVED  reserved_at_e00
 /* Calculate the fte_match_param length and without the reserved length.
  * Make sure the reserved field is the last.
  */
index 9c25edfd59a67693f556b5acf1347725bbe1326d..604b85dd770a4b064eef2d8fa844142aa3518a3b 100644 (file)
@@ -1117,6 +1117,7 @@ enum {
        MLX5_MATCH_MISC_PARAMETERS_2    = 1 << 3,
        MLX5_MATCH_MISC_PARAMETERS_3    = 1 << 4,
        MLX5_MATCH_MISC_PARAMETERS_4    = 1 << 5,
+       MLX5_MATCH_MISC_PARAMETERS_5    = 1 << 6,
 };
 
 enum {
index 18b816b41545c509081cbe5b0919c9e27d370681..c74c5e147cb90aaff1d48b29347f9cd08864af85 100644 (file)
@@ -670,6 +670,26 @@ struct mlx5_ifc_fte_match_set_misc4_bits {
        u8         reserved_at_100[0x100];
 };
 
+struct mlx5_ifc_fte_match_set_misc5_bits {
+       u8         macsec_tag_0[0x20];
+
+       u8         macsec_tag_1[0x20];
+
+       u8         macsec_tag_2[0x20];
+
+       u8         macsec_tag_3[0x20];
+
+       u8         tunnel_header_0[0x20];
+
+       u8         tunnel_header_1[0x20];
+
+       u8         tunnel_header_2[0x20];
+
+       u8         tunnel_header_3[0x20];
+
+       u8         reserved_at_100[0x100];
+};
+
 struct mlx5_ifc_cmd_pas_bits {
        u8         pa_h[0x20];
 
@@ -1839,7 +1859,9 @@ struct mlx5_ifc_fte_match_param_bits {
 
        struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
 
-       u8         reserved_at_c00[0x400];
+       struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
+
+       u8         reserved_at_e00[0x200];
 };
 
 enum {
@@ -5977,6 +5999,7 @@ enum {
        MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
        MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
        MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
+       MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
 };
 
 struct mlx5_ifc_query_flow_group_out_bits {
index ca2372864b70e961be3ac538597390d768a74db9..e539c84d63f1a08d7524c4b93f26e3e9ebb638f8 100644 (file)
@@ -252,7 +252,7 @@ enum mlx5_ib_device_query_context_attrs {
        MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX = (1U << UVERBS_ID_NS_SHIFT),
 };
 
-#define MLX5_IB_DW_MATCH_PARAM 0x90
+#define MLX5_IB_DW_MATCH_PARAM 0xA0
 
 struct mlx5_ib_match_params {
        __u32   match_params[MLX5_IB_DW_MATCH_PARAM];