drm/amdgpu: add gfx v9.4.3 ACA support

v1:
add gfx v9.4.3 ACA driver support

v2:
use macro to define smn address value.

Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 131cddbdda0dc11716205307e51d72aa72b271bf..f06e248bece03833d8cab7e1a0129e779360b121 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -38,6 +38,7 @@
 
 #include "gfx_v9_4_3.h"
 #include "amdgpu_xcp.h"
+#include "amdgpu_aca.h"
 
 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin");
 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin");
@@ -48,6 +49,10 @@ MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin");
 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042
 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301
 
+#define mmSMNAID_XCD0_MCA_SMU 0x36430400       /* SMN AID XCD0 */
+#define mmSMNAID_XCD1_MCA_SMU 0x38430400       /* SMN AID XCD1 */
+#define mmSMNXCD_XCD0_MCA_SMU 0x40430400       /* SMN XCD XCD0 */
+
 struct amdgpu_gfx_ras gfx_v9_4_3_ras;
 
 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev);
@@ -675,6 +680,66 @@ static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = {
        .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst,
 };
 
+static int gfx_v9_4_3_aca_bank_generate_report(struct aca_handle *handle,
+                                              struct aca_bank *bank, enum aca_error_type type,
+                                              struct aca_bank_report *report, void *data)
+{
+       u64 status, misc0;
+       u32 instlo;
+       int ret;
+
+       status = bank->regs[ACA_REG_IDX_STATUS];
+       if ((type == ACA_ERROR_TYPE_UE &&
+            ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_FAULT) ||
+           (type == ACA_ERROR_TYPE_CE &&
+            ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_CE)) {
+
+               ret = aca_bank_info_decode(bank, &report->info);
+               if (ret)
+                       return ret;
+
+               /* NOTE: overwrite info.die_id with xcd id for gfx */
+               instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
+               instlo &= GENMASK(31, 1);
+               report->info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1;
+
+               misc0 = bank->regs[ACA_REG_IDX_MISC0];
+               report->count[type] = ACA_REG__MISC0__ERRCNT(misc0);
+       }
+
+       return 0;
+}
+
+static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
+                                        enum aca_error_type type, void *data)
+{
+       u32 instlo;
+
+       instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
+       instlo &= GENMASK(31, 1);
+       switch (instlo) {
+       case mmSMNAID_XCD0_MCA_SMU:
+       case mmSMNAID_XCD1_MCA_SMU:
+       case mmSMNXCD_XCD0_MCA_SMU:
+               return true;
+       default:
+               break;
+       }
+
+       return false;
+}
+
+static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = {
+       .aca_bank_generate_report = gfx_v9_4_3_aca_bank_generate_report,
+       .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid,
+};
+
+static const struct aca_info gfx_v9_4_3_aca_info = {
+       .hwip = ACA_HWIP_TYPE_SMU,
+       .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK,
+       .bank_ops = &gfx_v9_4_3_aca_bank_ops,
+};
+
 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev)
 {
        u32 gb_addr_config;
@@ -4242,9 +4307,32 @@ struct amdgpu_ras_block_hw_ops  gfx_v9_4_3_ras_ops = {
        .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count,
 };
 
+static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
+{
+       int r;
+
+       r = amdgpu_ras_block_late_init(adev, ras_block);
+       if (r)
+               return r;
+
+       r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX,
+                               &gfx_v9_4_3_aca_info,
+                               NULL);
+       if (r)
+               goto late_fini;
+
+       return 0;
+
+late_fini:
+       amdgpu_ras_block_late_fini(adev, ras_block);
+
+       return r;
+}
+
 struct amdgpu_gfx_ras gfx_v9_4_3_ras = {
        .ras_block = {
                .hw_ops = &gfx_v9_4_3_ras_ops,
+               .ras_late_init = &gfx_v9_4_3_ras_late_init,
        },
        .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer,
 };