crypto: arm/sha512-neon - avoid ADRL pseudo instruction

The ADRL pseudo instruction is not an architectural construct, but a
convenience macro that was supported by the ARM proprietary assembler
and adopted by binutils GAS as well, but only when assembling in 32-bit
ARM mode. Therefore, it can only be used in assembler code that is known
to assemble in ARM mode only, but as it turns out, the Clang assembler
does not implement ADRL at all, and so it is better to get rid of it
entirely.

So replace the ADRL instruction with a ADR instruction that refers to
a nearer symbol, and apply the delta explicitly using an additional
instruction.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Tested-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/arch/arm/crypto/sha512-armv4.pl b/arch/arm/crypto/sha512-armv4.pl
index 69df68981acd5d7140f363e06a136ae32924c71e..2fc3516912fa59e948c99f2bd7e6c84672d6506e 100644 (file)
--- a/arch/arm/crypto/sha512-armv4.pl
+++ b/arch/arm/crypto/sha512-armv4.pl
@@ -212,7 +212,6 @@ $code=<<___;
 #else
 .syntax unified
 # ifdef __thumb2__
-#  define adrl adr
 .thumb
 # else
 .code   32
@@ -602,7 +601,8 @@ sha512_block_data_order_neon:
        dmb                             @ errata #451034 on early Cortex A8
        add     $len,$inp,$len,lsl#7    @ len to point at the end of inp
        VFP_ABI_PUSH
-       adrl    $Ktbl,K512
+       adr     $Ktbl,.Lsha512_block_data_order
+       sub     $Ktbl,$Ktbl,.Lsha512_block_data_order-K512
        vldmia  $ctx,{$A-$H}            @ load context
 .Loop_neon:
 ___

diff --git a/arch/arm/crypto/sha512-core.S_shipped b/arch/arm/crypto/sha512-core.S_shipped
index cb147db5cbfe903affcf975c314710de3d2735d4..03014624f2ab5c65a15bc9684065ce5d10238cdf 100644 (file)
--- a/arch/arm/crypto/sha512-core.S_shipped
+++ b/arch/arm/crypto/sha512-core.S_shipped
@@ -79,7 +79,6 @@
 #else
 .syntax unified
 # ifdef __thumb2__
-#  define adrl adr
 .thumb
 # else
 .code   32
@@ -543,7 +542,8 @@ sha512_block_data_order_neon:
        dmb                             @ errata #451034 on early Cortex A8
        add     r2,r1,r2,lsl#7  @ len to point at the end of inp
        VFP_ABI_PUSH
-       adrl    r3,K512
+       adr     r3,.Lsha512_block_data_order
+       sub     r3,r3,.Lsha512_block_data_order-K512
        vldmia  r0,{d16-d23}            @ load context
 .Loop_neon:
        vshr.u64        d24,d20,#14     @ 0