drm/i915/mtl: end support for set caching ioctl

The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
cache. For userspace components needing to fine tune the caching policy
for BO's, a follow up patch will extend the GEM_CREATE uAPI to allow
them specify caching mode at BO creation time.

Signed-off-by: Fei Yang <fei.yang@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230519051103.3404990-2-fei.yang@intel.com

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 05107a6efe450317fc313a657ffd6b69d8f075c8..dfaaa8b66ac30c0c17698005b4be703617828b54 100644 (file)
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -350,6 +350,9 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
        if (IS_DGFX(i915))
                return -ENODEV;
 
+       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+               return -EOPNOTSUPP;
+
        switch (args->caching) {
        case I915_CACHING_NONE:
                level = I915_CACHE_NONE;

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 37d1efcd3ca66880c09ab5d7863cd093abac27c0..cad4a6017f4b52e5ce5abc8379e1c07c7f6cf520 100644 (file)
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -601,7 +601,14 @@ static int shmem_object_init(struct intel_memory_region *mem,
        obj->write_domain = I915_GEM_DOMAIN_CPU;
        obj->read_domains = I915_GEM_DOMAIN_CPU;
 
-       if (HAS_LLC(i915))
+       /*
+        * MTL doesn't snoop CPU cache by default for GPU access (namely
+        * 1-way coherency). However some UMD's are currently depending on
+        * that. Make 1-way coherent the default setting for MTL. A follow
+        * up patch will extend the GEM_CREATE uAPI to allow UMD's specify
+        * caching mode at BO creation time
+        */
+       if (HAS_LLC(i915) || (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)))
                /* On some devices, we can have the GPU use the LLC (the CPU
                 * cache) for about a 10% performance improvement
                 * compared to uncached.  Graphics requests other than