ARM: dts: socfpga: change qspi to "intel,socfpga-qspi"

commit 36de991e93908f7ad5c2a0eac9c4ecf8b723fa4a upstream.

Because of commit 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling"),
which does a write to the CQSPI_REG_WR_COMPLETION_CTRL register
regardless of any condition. Well, the Cadence QuadSPI controller on
Intel's SoCFPGA platforms does not implement the
CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
results in a crash!

So starting with v5.16, I introduced the patch
98d948eb833 ("spi: cadence-quadspi: fix write completion support"),
which adds the dts compatible "intel,socfpga-qspi" that is specific for
versions that doesn't have the CQSPI_REG_WR_COMPLETION_CTRL register implemented.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
[IA: submitted for linux-5.15.y]
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 0b021eef0b5389e211e82a44b23ce10c4555e2b4..7c1d6423d7f8c6ed159c44a3efe6394ab9dae52b 100644 (file)
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -782,7 +782,7 @@
                };
 
                qspi: spi@ff705000 {
-                       compatible = "cdns,qspi-nor";
+                       compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0xff705000 0x1000>,

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index a574ea91d9d3f1894b82e508018bdc338b8dfa38..3ba431dfa8c9445c4767d674771a44e944fe9be4 100644 (file)
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -756,7 +756,7 @@
                };
 
                qspi: spi@ff809000 {
-                       compatible = "cdns,qspi-nor";
+                       compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0xff809000 0x100>,

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index d301ac0d406bf3f30fd6137b64c75a1fdc007d24..3ec301bd08a9158c89b6346e41404205002efdae 100644 (file)
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -594,7 +594,7 @@
                };
 
                qspi: spi@ff8d2000 {
-                       compatible = "cdns,qspi-nor";
+                       compatible =  "intel,socfpga-qspi", "cdns,qspi-nor";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0xff8d2000 0x100>,

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index de1e98c99ec5b21b5662ce653180ea05512fd66d..f4270cf1899624ca4722ac3a412288fa9ee6dfb2 100644 (file)
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -628,7 +628,7 @@
                };
 
                qspi: spi@ff8d2000 {
-                       compatible = "cdns,qspi-nor";
+                       compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0xff8d2000 0x100>,