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arm64: dts: renesas: r8a779h0: Add RWDT node
author
Minh Le
<minh.le.aj@renesas.com>
Thu, 1 Feb 2024 14:09:16 +0000
(15:09 +0100)
committer
Geert Uytterhoeven
<geert+renesas@glider.be>
Tue, 6 Feb 2024 09:46:39 +0000
(10:46 +0100)
Add a device node for the RCLK Watchdog Timer (RWDT) on the Renesas
R-Car V4M (R8A779H0) SoC.
Signed-off-by: Minh Le <minh.le.aj@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link:
https://lore.kernel.org/r/43bb03f3baa87b4be8ce953b1955df6b89387e4c.1706790320.git.geert+renesas@glider.be
arch/arm64/boot/dts/renesas/r8a779h0.dtsi
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diff --git
a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
index a082e2d06b696019a9ae706802e94f67b407713c..9ad53e85cf6068a94eb26730cd4872816fd1f4e5 100644
(file)
--- a/
arch/arm64/boot/dts/renesas/r8a779h0.dtsi
+++ b/
arch/arm64/boot/dts/renesas/r8a779h0.dtsi
@@
-59,6
+59,17
@@
#size-cells = <2>;
ranges;
+ rwdt: watchdog@e6020000 {
+ compatible = "renesas,r8a779h0-wdt",
+ "renesas,rcar-gen4-wdt";
+ reg = <0 0xe6020000 0 0x0c>;
+ interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+ resets = <&cpg 907>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a779h0-cpg-mssr";
reg = <0 0xe6150000 0 0x4000>;