accel/habanalabs: improve etf configuration

coresight ETF blocks have different size. As a result, sync packets
need to be aligned based on fifo size.

Signed-off-by: Benjamin Dotan <bdotan@habana.ai>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>

diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c b/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c
index 32e0f1a85b352bc1520c5536d57a520c9371c172..14a855cdc96b6e7f4f1c47401dcde49d7ac534f5 100644 (file)
--- a/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c
@@ -2125,10 +2125,17 @@ static int gaudi2_config_etf(struct hl_device *hdev, struct hl_debug_params *par
                if (!input)
                        return -EINVAL;
 
+               val = RREG32(base_reg + mmETF_RSZ_OFFSET) << 2;
+               if (val) {
+                       val = ffs(val);
+                       WREG32(base_reg + mmETF_PSCR_OFFSET, val);
+               } else {
+                       WREG32(base_reg + mmETF_PSCR_OFFSET, 0x10);
+               }
+
                WREG32(base_reg + mmETF_BUFWM_OFFSET, 0x3FFC);
                WREG32(base_reg + mmETF_MODE_OFFSET, input->sink_mode);
                WREG32(base_reg + mmETF_FFCR_OFFSET, 0x4001);
-               WREG32(base_reg + mmETF_PSCR_OFFSET, 0x10);
                WREG32(base_reg + mmETF_CTL_OFFSET, 1);
        } else {
                WREG32(base_reg + mmETF_BUFWM_OFFSET, 0);