drm/amd/display: Check if modulo is 0 before dividing.

[ Upstream commit 49947b906a6bd9668eaf4f9cf691973c25c26955 ]

[How & Why]
If a value of 0 is read, then this will cause a divide-by-0 panic.

Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 2c7eb982eabcabf7164fc802769220c3d43238bc..054823d12403d7cba5960d5225ff9ecfc06f3347 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -1013,9 +1013,12 @@ static bool get_pixel_clk_frequency_100hz(
                         * not be programmed equal to DPREFCLK
                         */
                        modulo_hz = REG_READ(MODULO[inst]);
-                       *pixel_clk_khz = div_u64((uint64_t)clock_hz*
-                               clock_source->ctx->dc->clk_mgr->dprefclk_khz*10,
-                               modulo_hz);
+                       if (modulo_hz)
+                               *pixel_clk_khz = div_u64((uint64_t)clock_hz*
+                                       clock_source->ctx->dc->clk_mgr->dprefclk_khz*10,
+                                       modulo_hz);
+                       else
+                               *pixel_clk_khz = 0;
                } else {
                        /* NOTE: There is agreement with VBIOS here that MODULO is
                         * programmed equal to DPREFCLK, in which case PHASE will be