clk: qcom: gcc-sm8550: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value for SM8550 is known and extracted from the msm-5.15 driver.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240105-topic-venus_reset-v2-12-c37eba13b5ce@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c
index b883dffe5f7aaa86ad903839ba2e42a3c4c5be70..4cbc728f5c724a96835631af4896b70fc4f79848 100644 (file)
--- a/drivers/clk/qcom/gcc-sm8550.c
+++ b/drivers/clk/qcom/gcc-sm8550.c
@@ -3276,8 +3276,8 @@ static const struct qcom_reset_map gcc_sm8550_resets[] = {
        [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
        [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
        [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
-       [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 },
-       [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32024, 2 },
+       [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 },
+       [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 },
        [GCC_VIDEO_BCR] = { 0x32000 },
 };