drm/amdgpu/mes: add helper function to get the ctx meta data offset
authorJack Xiao <Jack.Xiao@amd.com>
Fri, 27 Mar 2020 09:42:01 +0000 (17:42 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 4 May 2022 14:43:52 +0000 (10:43 -0400)
Add the helper function to get the corresponding ctx meta data offset.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

index 8cb74d0d0a1fcabac036379bdb83f8b0d8dc738a..4e99adcfbb0ef7256288d4284f0a034594930ed6 100644 (file)
@@ -717,3 +717,39 @@ amdgpu_mes_ring_to_queue_props(struct amdgpu_device *adev,
        props->paging = false;
        props->ring = ring;
 }
+
+#define DEFINE_AMDGPU_MES_CTX_GET_OFFS_ENG(_eng)                       \
+do {                                                                   \
+       if (id_offs < AMDGPU_MES_CTX_MAX_OFFS)                          \
+               return offsetof(struct amdgpu_mes_ctx_meta_data,        \
+                               _eng[ring->idx].slots[id_offs]);        \
+       else if (id_offs == AMDGPU_MES_CTX_RING_OFFS)                   \
+               return offsetof(struct amdgpu_mes_ctx_meta_data,        \
+                               _eng[ring->idx].ring);                  \
+       else if (id_offs == AMDGPU_MES_CTX_IB_OFFS)                     \
+               return offsetof(struct amdgpu_mes_ctx_meta_data,        \
+                               _eng[ring->idx].ib);                    \
+       else if (id_offs == AMDGPU_MES_CTX_PADDING_OFFS)                        \
+               return offsetof(struct amdgpu_mes_ctx_meta_data,        \
+                               _eng[ring->idx].padding);               \
+} while(0)
+
+int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs)
+{
+       switch (ring->funcs->type) {
+       case AMDGPU_RING_TYPE_GFX:
+               DEFINE_AMDGPU_MES_CTX_GET_OFFS_ENG(gfx);
+               break;
+       case AMDGPU_RING_TYPE_COMPUTE:
+               DEFINE_AMDGPU_MES_CTX_GET_OFFS_ENG(compute);
+               break;
+       case AMDGPU_RING_TYPE_SDMA:
+               DEFINE_AMDGPU_MES_CTX_GET_OFFS_ENG(sdma);
+               break;
+       default:
+               break;
+       }
+
+       WARN_ON(1);
+       return -EINVAL;
+}
index 1174c8d359ba7c22632aea6d03b5d535fd5ceb34..4c88e92b196f0c067431955907bbc83e2f0d4e0a 100644 (file)
@@ -231,9 +231,10 @@ struct amdgpu_mes_funcs {
                           struct mes_resume_gang_input *input);
 };
 
-
 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev))
 
+int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs);
+
 int amdgpu_mes_init(struct amdgpu_device *adev);
 void amdgpu_mes_fini(struct amdgpu_device *adev);