powerpc/8xx: Remove now unused TLB miss functions

The code to setup linear and IMMR mapping via huge TLB entries is
not called anymore. Remove it.

Also remove the handling of removed code exits in the perf driver.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/75750d25849cb8e73ca519866bb892d7eb9649c0.1589866984.git.christophe.leroy@csgroup.eu

diff --git a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
index 4d3ef3841b007ccad0195a2aa97888d17a9b3967..e82368838416eae426837c64bc38213db0e9d03e 100644 (file)
--- a/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
+++ b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h
@@ -240,13 +240,7 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
 }
 
 /* patch sites */
-extern s32 patch__itlbmiss_linmem_top, patch__itlbmiss_linmem_top8;
-extern s32 patch__dtlbmiss_linmem_top, patch__dtlbmiss_immr_jmp;
-extern s32 patch__fixupdar_linmem_top;
-extern s32 patch__dtlbmiss_romem_top, patch__dtlbmiss_romem_top8;
-
-extern s32 patch__itlbmiss_exit_1, patch__itlbmiss_exit_2;
-extern s32 patch__dtlbmiss_exit_1, patch__dtlbmiss_exit_2, patch__dtlbmiss_exit_3;
+extern s32 patch__itlbmiss_exit_1, patch__dtlbmiss_exit_1;
 extern s32 patch__itlbmiss_perf, patch__dtlbmiss_perf;
 
 #endif /* !__ASSEMBLY__ */

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index d1546f37975758980da337d0c92c0a8592363fc8..fb5d171877725546971419d3c1a55535371833a7 100644 (file)
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -278,33 +278,6 @@ InstructionTLBMiss:
        rfi
 #endif
 
-#ifndef CONFIG_PIN_TLB_TEXT
-ITLBMissLinear:
-       mtcr    r11
-#if defined(CONFIG_STRICT_KERNEL_RWX) && CONFIG_ETEXT_SHIFT < 23
-       patch_site      0f, patch__itlbmiss_linmem_top8
-
-       mfspr   r10, SPRN_SRR0
-0:     subis   r11, r10, (PAGE_OFFSET - 0x80000000)@ha
-       rlwinm  r11, r11, 4, MI_PS8MEG ^ MI_PS512K
-       ori     r11, r11, MI_PS512K | MI_SVALID
-       rlwinm  r10, r10, 0, 0x0ff80000 /* 8xx supports max 256Mb RAM */
-#else
-       /* Set 8M byte page and mark it valid */
-       li      r11, MI_PS8MEG | MI_SVALID
-       rlwinm  r10, r10, 20, 0x0f800000        /* 8xx supports max 256Mb RAM */
-#endif
-       mtspr   SPRN_MI_TWC, r11
-       ori     r10, r10, 0xf0 | MI_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
-                         _PAGE_PRESENT
-       mtspr   SPRN_MI_RPN, r10        /* Update TLB entry */
-
-0:     mfspr   r10, SPRN_SPRG_SCRATCH0
-       mfspr   r11, SPRN_SPRG_SCRATCH1
-       rfi
-       patch_site      0b, patch__itlbmiss_exit_2
-#endif
-
        . = 0x1200
 DataStoreTLBMiss:
        mtspr   SPRN_DAR, r10
@@ -371,62 +344,6 @@ DataStoreTLBMiss:
        rfi
        patch_site      0b, patch__dtlbmiss_exit_1
 
-DTLBMissIMMR:
-       mtcr    r11
-       /* Set 512k byte guarded page and mark it valid */
-       li      r10, MD_PS512K | MD_GUARDED | MD_SVALID
-       mtspr   SPRN_MD_TWC, r10
-       mfspr   r10, SPRN_IMMR                  /* Get current IMMR */
-       rlwinm  r10, r10, 0, 0xfff80000         /* Get 512 kbytes boundary */
-       ori     r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
-                         _PAGE_PRESENT | _PAGE_NO_CACHE
-       mtspr   SPRN_MD_RPN, r10        /* Update TLB entry */
-
-       li      r11, RPN_PATTERN
-
-0:     mfspr   r10, SPRN_DAR
-       mtspr   SPRN_DAR, r11   /* Tag DAR */
-       mfspr   r11, SPRN_M_TW
-       rfi
-       patch_site      0b, patch__dtlbmiss_exit_2
-
-DTLBMissLinear:
-       mtcr    r11
-       rlwinm  r10, r10, 20, 0x0f800000        /* 8xx supports max 256Mb RAM */
-#if defined(CONFIG_STRICT_KERNEL_RWX) && CONFIG_DATA_SHIFT < 23
-       patch_site      0f, patch__dtlbmiss_romem_top8
-
-0:     subis   r11, r10, (PAGE_OFFSET - 0x80000000)@ha
-       rlwinm  r11, r11, 0, 0xff800000
-       neg     r10, r11
-       or      r11, r11, r10
-       rlwinm  r11, r11, 4, MI_PS8MEG ^ MI_PS512K
-       ori     r11, r11, MI_PS512K | MI_SVALID
-       mfspr   r10, SPRN_MD_EPN
-       rlwinm  r10, r10, 0, 0x0ff80000 /* 8xx supports max 256Mb RAM */
-#else
-       /* Set 8M byte page and mark it valid */
-       li      r11, MD_PS8MEG | MD_SVALID
-#endif
-       mtspr   SPRN_MD_TWC, r11
-#ifdef CONFIG_STRICT_KERNEL_RWX
-       patch_site      0f, patch__dtlbmiss_romem_top
-
-0:     subis   r11, r10, 0
-       rlwimi  r10, r11, 11, _PAGE_RO
-#endif
-       ori     r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
-                         _PAGE_PRESENT
-       mtspr   SPRN_MD_RPN, r10        /* Update TLB entry */
-
-       li      r11, RPN_PATTERN
-
-0:     mfspr   r10, SPRN_DAR
-       mtspr   SPRN_DAR, r11   /* Tag DAR */
-       mfspr   r11, SPRN_M_TW
-       rfi
-       patch_site      0b, patch__dtlbmiss_exit_3
-
 /* This is an instruction TLB error on the MPC8xx.  This could be due
  * to many reasons, such as executing guarded memory or illegal instruction
  * addresses.  There is nothing to do but handle a big time error fault.

diff --git a/arch/powerpc/perf/8xx-pmu.c b/arch/powerpc/perf/8xx-pmu.c
index acc27fc63eb744e82baacfe0cb2557b5f461a575..e53c3c16125799ff225ba94504622bc4fb48b785 100644 (file)
--- a/arch/powerpc/perf/8xx-pmu.c
+++ b/arch/powerpc/perf/8xx-pmu.c
@@ -100,9 +100,6 @@ static int mpc8xx_pmu_add(struct perf_event *event, int flags)
                        unsigned long target = patch_site_addr(&patch__itlbmiss_perf);
 
                        patch_branch_site(&patch__itlbmiss_exit_1, target, 0);
-#ifndef CONFIG_PIN_TLB_TEXT
-                       patch_branch_site(&patch__itlbmiss_exit_2, target, 0);
-#endif
                }
                val = itlb_miss_counter;
                break;
@@ -111,8 +108,6 @@ static int mpc8xx_pmu_add(struct perf_event *event, int flags)
                        unsigned long target = patch_site_addr(&patch__dtlbmiss_perf);
 
                        patch_branch_site(&patch__dtlbmiss_exit_1, target, 0);
-                       patch_branch_site(&patch__dtlbmiss_exit_2, target, 0);
-                       patch_branch_site(&patch__dtlbmiss_exit_3, target, 0);
                }
                val = dtlb_miss_counter;
                break;
@@ -175,9 +170,6 @@ static void mpc8xx_pmu_del(struct perf_event *event, int flags)
                                            __PPC_SPR(SPRN_SPRG_SCRATCH0));
 
                        patch_instruction_site(&patch__itlbmiss_exit_1, insn);
-#ifndef CONFIG_PIN_TLB_TEXT
-                       patch_instruction_site(&patch__itlbmiss_exit_2, insn);
-#endif
                }
                break;
        case PERF_8xx_ID_DTLB_LOAD_MISS:
@@ -187,8 +179,6 @@ static void mpc8xx_pmu_del(struct perf_event *event, int flags)
                                            __PPC_SPR(SPRN_DAR));
 
                        patch_instruction_site(&patch__dtlbmiss_exit_1, insn);
-                       patch_instruction_site(&patch__dtlbmiss_exit_2, insn);
-                       patch_instruction_site(&patch__dtlbmiss_exit_3, insn);
                }
                break;
        }