wifi: iwlwifi: Force SCU_ACTIVE for specific platforms
authorDaniel Gabay <daniel.gabay@intel.com>
Mon, 6 May 2024 07:04:14 +0000 (10:04 +0300)
committerJohannes Berg <johannes.berg@intel.com>
Mon, 6 May 2024 14:33:26 +0000 (16:33 +0200)
Firmware 0x2F7 assert observed in Dell platforms when using GL HW.
This issue is mitigated by setting SCU_FORCE_ACTIVE during platform
low power states.

Driver shall indicate firmware to force SCU active by setting bit 29
in context info prph scratch control flags.
This mitigation is limited to Dell platforms with GL HW only.

Signed-off-by: Daniel Gabay <daniel.gabay@intel.com>
Reviewed-by: Ofer Kimelman <ofer.kimelman@intel.com>
Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com>
Link: https://msgid.link/20240506095953.3d0c56c2bb1a.I97d9da402890d2085b5698666cceffc417b6b6df@changeid
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
drivers/net/wireless/intel/iwlwifi/iwl-context-info-gen3.h
drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info-gen3.c

index 1379dc2d231bf17e3d2d0ecd0260687d7f9d04f5..5b62933134cf4658e64a2e8ff315c1dbfca60e41 100644 (file)
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 /*
- * Copyright (C) 2018, 2020-2023 Intel Corporation
+ * Copyright (C) 2018, 2020-2024 Intel Corporation
  */
 #ifndef __iwl_context_info_file_gen3_h__
 #define __iwl_context_info_file_gen3_h__
@@ -56,6 +56,8 @@ enum iwl_prph_scratch_mtr_format {
  * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size
  * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size
  * @IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size
+ * @IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE: Indicate fw to set SCU_FORCE_ACTIVE
+ *     upon reset.
  */
 enum iwl_prph_scratch_flags {
        IWL_PRPH_SCRATCH_IMR_DEBUG_EN           = BIT(1),
@@ -71,6 +73,7 @@ enum iwl_prph_scratch_flags {
        IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K         = 8 << 20,
        IWL_PRPH_SCRATCH_RB_SIZE_EXT_12K        = 9 << 20,
        IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K        = 10 << 20,
+       IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE       = BIT(29),
 };
 
 /*
index c8fc8b4fd85c7a9f9647efcc9e5e3ce6fac83527..ebf11f276b20a13bcf65e653bfd0e0a26b1752d2 100644 (file)
@@ -1,13 +1,34 @@
 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
- * Copyright (C) 2018-2023 Intel Corporation
+ * Copyright (C) 2018-2024 Intel Corporation
  */
+#include <linux/dmi.h>
 #include "iwl-trans.h"
 #include "iwl-fh.h"
 #include "iwl-context-info-gen3.h"
 #include "internal.h"
 #include "iwl-prph.h"
 
+static const struct dmi_system_id dmi_force_scu_active_approved_list[] = {
+       { .ident = "DELL",
+         .matches = {
+                       DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
+               },
+       },
+       { .ident = "DELL",
+         .matches = {
+                       DMI_MATCH(DMI_SYS_VENDOR, "Alienware"),
+               },
+       },
+       /* keep last */
+       {}
+};
+
+static bool iwl_is_force_scu_active_approved(void)
+{
+       return !!dmi_check_system(dmi_force_scu_active_approved_list);
+}
+
 static void
 iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans,
                              struct iwl_prph_scratch_hwm_cfg *dbg_cfg,
@@ -128,6 +149,14 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
        if (trans->trans_cfg->imr_enabled)
                control_flags |= IWL_PRPH_SCRATCH_IMR_DEBUG_EN;
 
+       if (CSR_HW_REV_TYPE(trans->hw_rev) == IWL_CFG_MAC_TYPE_GL &&
+           iwl_is_force_scu_active_approved()) {
+               control_flags |= IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE;
+               IWL_DEBUG_FW(trans,
+                            "Context Info: Set SCU_FORCE_ACTIVE (0x%x) in control_flags\n",
+                            IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE);
+       }
+
        /* initialize RX default queue */
        prph_sc_ctrl->rbd_cfg.free_rbd_addr =
                cpu_to_le64(trans_pcie->rxq->bd_dma);