target/riscv: Add a property to set vl to ceil(AVL/2)
authorJason Chien <jason.chien@sifive.com>
Mon, 22 Jul 2024 17:50:04 +0000 (01:50 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 2 Oct 2024 05:11:51 +0000 (15:11 +1000)
RVV spec allows implementations to set vl with values within
[ceil(AVL/2),VLMAX] when VLMAX < AVL < 2*VLMAX. This commit adds a
property "rvv_vl_half_avl" to enable setting vl = ceil(AVL/2). This
behavior helps identify compiler issues and bugs.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-ID: <20240722175004.23666-1-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu_cfg.h
target/riscv/vector_helper.c

index 4bda754b01304e02b0cb013ee2aef764fb8c0dc9..cc5552500af0beeee9dab8e000675b8d2cac8e71 100644 (file)
@@ -2661,6 +2661,7 @@ static Property riscv_cpu_properties[] = {
 
     DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
     DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
+    DEFINE_PROP_BOOL("rvv_vl_half_avl", RISCVCPU, cfg.rvv_vl_half_avl, false),
 
     /*
      * write_misa() is marked as experimental for now so mark
index 8b272fb826efe31173e3cfd0d407f4c526be0564..96fe26d4eac499f5791ae14e189d75c70a005021 100644 (file)
@@ -127,6 +127,7 @@ struct RISCVCPUConfig {
     bool ext_smepmp;
     bool rvv_ta_all_1s;
     bool rvv_ma_all_1s;
+    bool rvv_vl_half_avl;
 
     uint32_t mvendorid;
     uint64_t marchid;
index 10a52ceb5b182cfb2c00e7e24820a49b1bc77002..072bd444b1dce161228c7ac385eb341f4b7351a1 100644 (file)
@@ -75,6 +75,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
     vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul);
     if (s1 <= vlmax) {
         vl = s1;
+    } else if (s1 < 2 * vlmax && cpu->cfg.rvv_vl_half_avl) {
+        vl = (s1 + 1) >> 1;
     } else {
         vl = vlmax;
     }