ARM: dts: nuvoton: Add Nuvoton NPCM730 device tree

The Nuvoton NPCN730 SoC is a part of the Nuvoton NPCM7xx SoCs family.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>

diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
new file mode 100644 (file)
index 0000000..86ec12e
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2020 Nuvoton Technology
+
+#include "nuvoton-common-npcm7xx.dtsi"
+
+/ {
+       #address-cells = <1>;
+       #size-cells = <1>;
+       interrupt-parent = <&gic>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               enable-method = "nuvoton,npcm750-smp";
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       clocks = <&clk NPCM7XX_CLK_CPU>;
+                       clock-names = "clk_cpu";
+                       reg = <0>;
+                       next-level-cache = <&l2>;
+               };
+
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       clocks = <&clk NPCM7XX_CLK_CPU>;
+                       clock-names = "clk_cpu";
+                       reg = <1>;
+                       next-level-cache = <&l2>;
+               };
+       };
+
+       soc {
+               timer@3fe600 {
+                       compatible = "arm,cortex-a9-twd-timer";
+                       reg = <0x3fe600 0x20>;
+                       interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+                                                 IRQ_TYPE_LEVEL_HIGH)>;
+                       clocks = <&clk NPCM7XX_CLK_AHB>;
+               };
+       };
+};