perf/x86/intel: Expose EPT-friendly PEBS for SPR and future models

According to Intel SDM, the EPT-friendly PEBS is supported by all the
platforms after ICX, ADL and the future platforms with PEBS format 5.

Currently the only in-kernel user of this capability is KVM, which has
very limited support for hybrid core pmu, so ADL and its successors do
not currently expose this capability. When both hybrid core and PEBS
format 5 are present, KVM will decide on its own merits.

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-perf-users@vger.kernel.org
Suggested-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Like Xu <likexu@tencent.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20221109082802.27543-4-likexu@tencent.com
Signed-off-by: Sean Christopherson <seanjc@google.com>

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index dfd2c124cdf80a819570340caa2b886887d57890..aa53d042b943ede2ef19909a7570b48be0fbda75 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -6348,6 +6348,7 @@ __init int intel_pmu_init(void)
                x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;
                x86_pmu.extra_regs = intel_spr_extra_regs;
                x86_pmu.limit_period = spr_limit_period;
+               x86_pmu.pebs_ept = 1;
                x86_pmu.pebs_aliases = NULL;
                x86_pmu.pebs_prec_dist = true;
                x86_pmu.pebs_block = true;

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 88e58b6ee73c016cd55a7eb887751778a6c5d086..d8a404b91b7eec10898e5cdf23d4758dff174da4 100644 (file)
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2303,8 +2303,10 @@ void __init intel_ds_init(void)
                        x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
                        break;
 
-               case 4:
                case 5:
+                       x86_pmu.pebs_ept = 1;
+                       fallthrough;
+               case 4:
                        x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl;
                        x86_pmu.pebs_record_size = sizeof(struct pebs_basic);
                        if (x86_pmu.intel_cap.pebs_baseline) {