drm/amd/display: [FW Promotion] Release 0.0.189.0

 - Minor formatting changes
 - Update defines to match the bit width of the field it is used for
 - Add new boot up bits to control HW sub block regions power
   down

Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Anthony Koo <anthony.koo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index bc907ae2052d5eea67506cac242316751b8310c6..61b4009c3b76f73cd4eeebc0d2f5bbe294860ecc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -583,6 +583,7 @@ union dmub_fw_boot_status {
                uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */
                uint32_t detection_required: 1; /**<  if detection need to be triggered by driver */
                uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */
+               uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */
        } bits; /**< status bits */
        uint32_t all; /**< 32-bit access to status bits */
 };
@@ -599,6 +600,7 @@ enum dmub_fw_boot_status_bit {
        DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/
        DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
        DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */
+       DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */
 };
 
 /* Register bit definition for SCRATCH5 */
@@ -2098,7 +2100,7 @@ enum psr_version {
        /**
         * PSR not supported.
         */
-       PSR_VERSION_UNSUPPORTED                 = 0xFFFFFFFF,
+       PSR_VERSION_UNSUPPORTED                 = 0xFF, // psr_version field is only 8 bits wide
 };
 
 /**
@@ -3620,7 +3622,6 @@ struct dmub_cmd_abm_pause_data {
        uint8_t pad[1];
 };
 
-
 /**
  * Definition of a DMUB_CMD__ABM_PAUSE command.
  */
@@ -4046,6 +4047,7 @@ union dmub_rb_cmd {
         * Definition of a DMUB_CMD__MALL command.
         */
        struct dmub_rb_cmd_mall mall;
+
        /**
         * Definition of a DMUB_CMD__CAB command.
         */
@@ -4067,6 +4069,7 @@ union dmub_rb_cmd {
         * Definition of DMUB_CMD__PANEL_CNTL commands.
         */
        struct dmub_rb_cmd_panel_cntl panel_cntl;
+
        /**
         * Definition of a DMUB_CMD__ABM_SET_PIPE command.
         */
@@ -4470,10 +4473,6 @@ static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
                uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr);
                uint8_t i;
 
-               /* Don't remove this.
-                * The contents need to actually be read from the ring buffer
-                * for this function to be effective.
-                */
                for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
                        (void)READ_ONCE(*data++);
 
@@ -4522,5 +4521,4 @@ static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
 //==============================================================================
 //</DMUB_RB>====================================================================
 //==============================================================================
-
 #endif /* _DMUB_CMD_H_ */