drm/i915: Replace several IS_METEORLAKE with proper IP version checks

Many of the IS_METEORLAKE conditions throughout the driver are supposed
to be checks for Xe_LPG and/or Xe_LPM+ IP, not for the MTL platform
specifically.  Update those checks to ensure that the code will still
operate properly if/when these IP versions show up on future platforms.

v2:
 - Update two more conditions (one for pg_enable, one for MTL HuC
   compatibility).
v3:
 - Don't change GuC/HuC compatibility check, which sounds like it truly
   is specific to the MTL platform.  (Gustavo)
 - Drop a non-lineage workaround number for the OA timestamp frequency
   workaround.  (Gustavo)

Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-20-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index d24c0ce8805c7056444d66374ed2c86cf14d93bc..19156ba4b9ef404e8944b94b0dbf87534dcad952 100644 (file)
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -405,8 +405,8 @@ static int ext_set_pat(struct i915_user_extension __user *base, void *data)
        BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
                     offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
 
-       /* Limiting the extension only to Meteor Lake */
-       if (!IS_METEORLAKE(i915))
+       /* Limiting the extension only to Xe_LPG and beyond */
+       if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 70))
                return -ENODEV;
 
        if (copy_from_user(&ext, base, sizeof(ext)))

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index b538b5c04948f63ee459411a10b246fe56c41c3b..e91fc881dbf18ba4e23147fa05e035ca41c41d68 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -21,7 +21,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine)
 {
        struct drm_i915_private *i915 = engine->i915;
 
-       if (IS_METEORLAKE(i915) && engine->id == GSC0) {
+       if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {
                intel_uncore_write(engine->gt->uncore,
                                   RC_PSMI_CTRL_GSCCS,
                                   _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index bf8b42d2d3279a8d3aba56d1026939fbb8d9a7fc..07269ff3be136deb23e34358e70a0a623411dc3c 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -495,7 +495,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
        memset(table, 0, sizeof(struct drm_i915_mocs_table));
 
        table->unused_entries_index = I915_MOCS_PTE;
-       if (IS_METEORLAKE(i915)) {
+       if (IS_GFX_GT_IP_RANGE(&i915->gt0, IP_VER(12, 70), IP_VER(12, 71))) {
                table->size = ARRAY_SIZE(mtl_mocs_table);
                table->table = mtl_mocs_table;
                table->n_entries = MTL_NUM_MOCS_ENTRIES;

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 86df42cb5823f78f207c4c4138bdb5af0243a02e..8b67abd720be866282b1c8b3946786c31186fe0a 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -123,7 +123,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
         * temporary wa and should be removed after fixing real cause
         * of forcewake timeouts.
         */
-       if (IS_METEORLAKE(gt->i915))
+       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
                pg_enable =
                        GEN9_MEDIA_PG_ENABLE |
                        GEN11_MEDIA_SAMPLER_PG_ENABLE;

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index fd6c22aeb670e1cb78483a9b3917baf777b627e2..98575d79c446638b163d447d3b64a96dd078761f 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -705,7 +705,7 @@ static int __reset_guc(struct intel_gt *gt)
 
 static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t engine_mask)
 {
-       if (!IS_METEORLAKE(gt->i915) || !HAS_ENGINE(gt, GSC0))
+       if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt, GSC0))
                return false;
 
        if (!__HAS_ENGINE(engine_mask, GSC0))

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 092542f53aad9c59d0fbdd4c73170c07c866ea09..4feef874e6d6958bcfe90e60f1aa28bc195a7848 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1161,7 +1161,7 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *c
 {
        struct drm_i915_private *i915 = rps_to_i915(rps);
 
-       if (IS_METEORLAKE(i915))
+       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
                return mtl_get_freq_caps(rps, caps);
        else
                return __gen6_rps_get_freq_caps(rps, caps);

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 4de44cf1026dcee0528771c71f6efd98e2d97345..7a90a2e32c9f1bb41a159aaa8e00b3a50475f593 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -144,7 +144,7 @@ static const char *i915_cache_level_str(struct drm_i915_gem_object *obj)
 {
        struct drm_i915_private *i915 = obj_to_i915(obj);
 
-       if (IS_METEORLAKE(i915)) {
+       if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) {
                switch (obj->pat_index) {
                case 0: return " WB";
                case 1: return " WT";

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 605e6e4fedf1b0111acfe4e3867cd91213ffd8ca..018f42fff4cc0c66bbf7db63c5ff8ed3effa8b19 100644 (file)
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3220,11 +3220,10 @@ get_sseu_config(struct intel_sseu *out_sseu,
  */
 u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
 {
-       /*
-        * Wa_18013179988:dg2
-        * Wa_14015846243:mtl
-        */
-       if (IS_DG2(i915) || IS_METEORLAKE(i915)) {
+       struct intel_gt *gt = to_gt(i915);
+
+       /* Wa_18013179988 */
+       if (IS_DG2(i915) || IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
                intel_wakeref_t wakeref;
                u32 reg, shift;
 
@@ -4507,7 +4506,7 @@ static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
 
 static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
 {
-       if (IS_METEORLAKE(perf->i915))
+       if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70))
                return reg_in_range_table(addr, mtl_oa_mux_regs);
        else
                return reg_in_range_table(addr, gen12_oa_mux_regs);