arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs

commit 8cae268b70f387ff9e697ccd62fb2384079124e7 upstream.

Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A53 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.

Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.

[1] https://developer.arm.com/documentation/ddi0500/e/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
[3] https://developer.arm.com/documentation/ddi0500/e/generic-interrupt-controller-cpu-interface/gic-programmers-model/memory-map

Cc: stable@vger.kernel.org # 5.10+
Fixes: ea47eed33a3f ("arm64: dts: ti: Add Support for AM654 SoC")
Reported-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220215201008.15235-2-nm@ti.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index ba4e5d3e1ed7a6d65f8a605d3a8556fa7f4c7a1d..82be00069bcd50262f93a2e42ae0a8c64c13e5d0 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -35,7 +35,10 @@
                #interrupt-cells = <3>;
                interrupt-controller;
                reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
-                     <0x00 0x01880000 0x00 0x90000>;   /* GICR */
+                     <0x00 0x01880000 0x00 0x90000>,   /* GICR */
+                     <0x00 0x6f000000 0x00 0x2000>,    /* GICC */
+                     <0x00 0x6f010000 0x00 0x1000>,    /* GICH */
+                     <0x00 0x6f020000 0x00 0x2000>;    /* GICV */
                /*
                 * vcpumntirq:
                 * virtual CPU interface maintenance interrupt

diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
index a9fc1af03f27f77bf1c78d5295a08415ce8bade4..1607db9b32dd2bdf29abb6870e8e09ce78b99aa1 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
@@ -84,6 +84,7 @@
                         <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
                         <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
                         <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
+                        <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
                         <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
                         <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
                         <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;