wifi: rtw89: 8852b: implement chip_ops::{enable,disable}_bb_rf
authorPing-Ke Shih <pkshih@realtek.com>
Tue, 27 Sep 2022 06:26:06 +0000 (14:26 +0800)
committerKalle Valo <kvalo@kernel.org>
Wed, 28 Sep 2022 06:45:58 +0000 (09:45 +0300)
Implement to power on/off BB and RF via MAC registers.

Add return type of chip_ops::disable_bb_rf, because it could fail to
disable. Also, correct naming of register 0x0200 used by the ops as well.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220927062611.30484-5-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/core.c
drivers/net/wireless/realtek/rtw89/core.h
drivers/net/wireless/realtek/rtw89/mac.c
drivers/net/wireless/realtek/rtw89/mac.h
drivers/net/wireless/realtek/rtw89/reg.h
drivers/net/wireless/realtek/rtw89/rtw8852b.c
drivers/net/wireless/realtek/rtw89/rtw8852c.c

index 7f75d05c004fb9e31a0f17925e66337dbd30dd09..31c2a7d6bfc2d6c0cb1930c9c6b4dc810f60019f 100644 (file)
@@ -2949,7 +2949,9 @@ int rtw89_core_start(struct rtw89_dev *rtwdev)
        /* efuse process */
 
        /* pre-config BB/RF, BB reset/RFC reset */
-       rtw89_chip_disable_bb_rf(rtwdev);
+       ret = rtw89_chip_disable_bb_rf(rtwdev);
+       if (ret)
+               return ret;
        ret = rtw89_chip_enable_bb_rf(rtwdev);
        if (ret)
                return ret;
index b8b143c528358537d6499b0e4aa5f148bb275d3a..d79e84f436c1a4660d8c8054a541e63151afb8b5 100644 (file)
@@ -2292,7 +2292,7 @@ struct rtw89_hci_info {
 
 struct rtw89_chip_ops {
        int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
-       void (*disable_bb_rf)(struct rtw89_dev *rtwdev);
+       int (*disable_bb_rf)(struct rtw89_dev *rtwdev);
        void (*bb_reset)(struct rtw89_dev *rtwdev,
                         enum rtw89_phy_idx phy_idx);
        void (*bb_sethw)(struct rtw89_dev *rtwdev);
index 9b75d9645580fe51dfb15b6abd20eaeee8273eba..30132c4583d7daa7c40938415669d273d921bd27 100644 (file)
@@ -1224,8 +1224,8 @@ static int chip_func_en(struct rtw89_dev *rtwdev)
 {
        enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
 
-       if (chip_id == RTL8852A)
-               rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL0,
+       if (chip_id == RTL8852A || chip_id == RTL8852B)
+               rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0,
                                  B_AX_OCP_L1_MASK);
 
        return 0;
@@ -3205,7 +3205,7 @@ int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
 }
 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf);
 
-void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
+int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
 {
        rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
                         B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
@@ -3213,6 +3213,8 @@ void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
                          B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 |
                          B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1);
        rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);
+
+       return 0;
 }
 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf);
 
index 5d1bb00a0fd2b2ff87a3e733095243ce3deb27ba..c09cc1f56ec1d94c350c748fcb067296afa2a4bf 100644 (file)
@@ -805,7 +805,7 @@ void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
                                        struct ieee80211_vif *vif);
 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
-void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);
+int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);
 
 static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev)
 {
@@ -814,11 +814,11 @@ static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev)
        return chip->ops->enable_bb_rf(rtwdev);
 }
 
-static inline void rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev)
+static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev)
 {
        const struct rtw89_chip_info *chip = rtwdev->chip;
 
-       chip->ops->disable_bb_rf(rtwdev);
+       return chip->ops->disable_bb_rf(rtwdev);
 }
 
 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
@@ -988,8 +988,10 @@ enum rtw89_mac_xtal_si_offset {
 #define XTAL_SI_HIGH_ADDR_MASK GENMASK(2, 0)
        XTAL_SI_READ_VAL = 0x7A,
        XTAL_SI_WL_RFC_S0 = 0x80,
+#define XTAL_SI_RF00S_EN       GENMASK(2, 0)
 #define XTAL_SI_RF00           BIT(0)
        XTAL_SI_WL_RFC_S1 = 0x81,
+#define XTAL_SI_RF10S_EN       GENMASK(2, 0)
 #define XTAL_SI_RF10           BIT(0)
        XTAL_SI_ANAPAR_WL = 0x90,
 #define XTAL_SI_SRAM2RFC       BIT(7)
index 9426b53e663bbb294e7dacb403a7536714d0c3d7..cb81c7eaece8a6bb38b8c68153b851326f61ade6 100644 (file)
@@ -51,9 +51,6 @@
 #define B_AX_EF_POR BIT(10)
 #define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8)
 
-#define R_AX_SPSLDO_ON_CTRL0 0x0200
-#define B_AX_OCP_L1_MASK GENMASK(15, 13)
-
 #define R_AX_EFUSE_CTRL 0x0030
 #define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30)
 #define B_AX_EF_RDY BIT(29)
 #define R_AX_UDM2 0x01F8
 #define R_AX_UDM3 0x01FC
 
+#define R_AX_SPS_DIG_ON_CTRL0 0x0200
+#define B_AX_VREFPFM_L_MASK GENMASK(25, 22)
+#define B_AX_REG_ZCDC_H_MASK GENMASK(18, 17)
+#define B_AX_OCP_L1_MASK GENMASK(15, 13)
+#define B_AX_VOL_L1_MASK GENMASK(3, 0)
+
 #define R_AX_LDO_AON_CTRL0 0x0218
 #define B_AX_PD_REGU_L BIT(16)
 
 
 #define R_AX_PHYREG_SET 0x8040
 #define PHYREG_SET_ALL_CYCLE 0x8
+#define PHYREG_SET_XYN_CYCLE 0xE
 
 #define R_AX_HD0IMR 0x8110
 #define B_AX_WDT_PTFM_INT_EN BIT(5)
index f951b8f0b5cfcf59c39371715d4899e46853ed38..799da0c9f75ad9601ec1c8cf835c7cb6cee98530 100644 (file)
@@ -3,6 +3,66 @@
  */
 
 #include "core.h"
+#include "mac.h"
+#include "reg.h"
+
+static int rtw8852b_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
+{
+       int ret;
+
+       rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
+                        B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
+       rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x1);
+       rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
+       rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
+       rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
+
+       ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7,
+                                     FULL_BIT_MASK);
+       if (ret)
+               return ret;
+
+       ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7,
+                                     FULL_BIT_MASK);
+       if (ret)
+               return ret;
+
+       rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE);
+
+       return 0;
+}
+
+static int rtw8852b_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
+{
+       u8 wl_rfc_s0;
+       u8 wl_rfc_s1;
+       int ret;
+
+       rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
+                        B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
+
+       ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0);
+       if (ret)
+               return ret;
+       wl_rfc_s0 &= ~XTAL_SI_RF00S_EN;
+       ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0,
+                                     FULL_BIT_MASK);
+       if (ret)
+               return ret;
+
+       ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1);
+       if (ret)
+               return ret;
+       wl_rfc_s1 &= ~XTAL_SI_RF10S_EN;
+       ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1,
+                                     FULL_BIT_MASK);
+       return ret;
+}
+
+static const struct rtw89_chip_ops rtw8852b_chip_ops = {
+       .enable_bb_rf           = rtw8852b_mac_enable_bb_rf,
+       .disable_bb_rf          = rtw8852b_mac_disable_bb_rf,
+};
 
 const struct rtw89_chip_info rtw8852b_chip_info = {
        .chip_id                = RTL8852B,
index 8c242d21e5fa4dd4795bc2a63094f700643530be..00462c912ec7ecf7e65ad1a390ea6c301c223800 100644 (file)
@@ -2976,10 +2976,12 @@ static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
        return 0;
 }
 
-static void rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
+static int rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
 {
        rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
                         B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
+
+       return 0;
 }
 
 static const struct rtw89_chip_ops rtw8852c_chip_ops = {