arm64: dts: qcom: sm8250: Add GPI DMA nodes

Add and configure GPI DMA nodes to enable the way for peripherals to make
DMA transfers.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210614235630.445501-3-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index f087f8837a5ea02d00d49be048b4adda0158520b..12217b3ce6b65dcacce2a7e9d1b898e09808bf10 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
 #include <dt-bindings/clock/qcom,gpucc-sm8250.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/interconnect/qcom,sm8250.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
@@ -519,6 +520,26 @@
                        };
                };
 
+               gpi_dma2: dma-controller@800000 {
+                       compatible = "qcom,sm8250-gpi-dma";
+                       reg = <0 0x00800000 0 0x70000>;
+                       interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
+                       dma-channels = <10>;
+                       dma-channel-mask = <0x3f>;
+                       iommus = <&apps_smmu 0x76 0x0>;
+                       #dma-cells = <3>;
+                       status = "disabled";
+               };
+
                qupv3_id_2: geniqup@8c0000 {
                        compatible = "qcom,geni-se-qup";
                        reg = <0x0 0x008c0000 0x0 0x6000>;
@@ -714,6 +735,29 @@
                        };
                };
 
+               gpi_dma0: dma-controller@900000 {
+                       compatible = "qcom,sm8250-gpi-dma";
+                       reg = <0 0x00900000 0 0x70000>;
+                       interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+                       dma-channels = <15>;
+                       dma-channel-mask = <0x7ff>;
+                       iommus = <&apps_smmu 0x5b6 0x0>;
+                       #dma-cells = <3>;
+                       status = "disabled";
+               };
+
                qupv3_id_0: geniqup@9c0000 {
                        compatible = "qcom,geni-se-qup";
                        reg = <0x0 0x009c0000 0x0 0x6000>;
@@ -961,6 +1005,26 @@
                        };
                };
 
+               gpi_dma1: dma-controller@a00000 {
+                       compatible = "qcom,sm8250-gpi-dma";
+                       reg = <0 0x00a00000 0 0x70000>;
+                       interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+                       dma-channels = <10>;
+                       dma-channel-mask = <0x3f>;
+                       iommus = <&apps_smmu 0x56 0x0>;
+                       #dma-cells = <3>;
+                       status = "disabled";
+               };
+
                qupv3_id_1: geniqup@ac0000 {
                        compatible = "qcom,geni-se-qup";
                        reg = <0x0 0x00ac0000 0x0 0x6000>;