ARM: dts: dra7: Use clksel binding for CM_CLKSEL_ABE_PLL_SYS

With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.

Let's also add a comment for the clocksel clock that matches the
documentation.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
index 2c037a8ce94eb2266a3070863c20e0649c547bb0..6328784797987bce9c812bb59baf2581b4944a12 100644 (file)
--- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
@@ -975,12 +975,21 @@
                ti,index-starts-at-one;
        };
 
-       abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 {
-               #clock-cells = <0>;
-               compatible = "ti,mux-clock";
-               clock-output-names = "abe_dpll_sys_clk_mux";
-               clocks = <&sys_clkin1>, <&sys_clkin2>;
-               reg = <0x0118>;
+       /* CM_CLKSEL_ABE_PLL_SYS */
+       clock@118 {
+               compatible = "ti,clksel";
+               reg = <0x118>;
+               #clock-cells = <2>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               abe_dpll_sys_clk_mux: clock@0 {
+                       reg = <0>;
+                       compatible = "ti,mux-clock";
+                       clock-output-names = "abe_dpll_sys_clk_mux";
+                       clocks = <&sys_clkin1>, <&sys_clkin2>;
+                       #clock-cells = <0>;
+               };
        };
 
        abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 {