ARM: dts: ixp4xx: Add PCI hosts

This adds a basic PCI host definition to the base device
tree for IXP4xx and then further details it in the 42x
and 43x device tree include, also the specific target
devices NSLU2 and GW2358 get proper PCI swizzling
defined.

Cc: Zoltan HERPAI <wigyori@uid0.hu>
Cc: Raylynn Knight <rayknight@me.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
index 8cacf035dc324a688aba2892c48b1e60039d7a8e..af9a2b0fe53990d9473a8be61929838aff2fde1b 100644 (file)
--- a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
+++ b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
@@ -108,6 +108,31 @@
        };
 
        soc {
+               pci@c0000000 {
+                       status = "ok";
+
+                       /*
+                        * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant
+                        * We have slots (IDSEL) 1, 2 and 3.
+                        */
+                       interrupt-map =
+                       /* IDSEL 1 */
+                       <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
+                       <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
+                       <0x0800 0 0 3 &gpio0 9  3>, /* INT C on slot 1 is irq 9 */
+                       <0x0800 0 0 4 &gpio0 8  3>, /* INT D on slot 1 is irq 8 */
+                       /* IDSEL 2 */
+                       <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
+                       <0x1000 0 0 2 &gpio0 9  3>, /* INT B on slot 2 is irq 9 */
+                       <0x1000 0 0 3 &gpio0 11 3>, /* INT C on slot 2 is irq 11 */
+                       <0x1000 0 0 4 &gpio0 8  3>, /* INT D on slot 2 is irq 8 */
+                       /* IDSEL 3 */
+                       <0x1800 0 0 1 &gpio0 9  3>, /* INT A on slot 3 is irq 9 */
+                       <0x1800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
+                       <0x1800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
+                       <0x1800 0 0 4 &gpio0 8  3>; /* INT D on slot 3 is irq 8 */
+               };
+
                ethernet@c8009000 {
                        status = "ok";
                        queue-rx = <&qmgr 3>;

diff --git a/arch/arm/boot/dts/intel-ixp42x.dtsi b/arch/arm/boot/dts/intel-ixp42x.dtsi
index a9622ca850ccc0dda872f25ddfc611142f96ce17..5fa063ed396cfe883844f84cd929edd05346afae 100644 (file)
--- a/arch/arm/boot/dts/intel-ixp42x.dtsi
+++ b/arch/arm/boot/dts/intel-ixp42x.dtsi
@@ -7,6 +7,10 @@
 
 / {
        soc {
+               pci@c0000000 {
+                       compatible = "intel,ixp42x-pci";
+               };
+
                interrupt-controller@c8003000 {
                        compatible = "intel,ixp42x-interrupt";
                };

diff --git a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
index f89d41b496ab23437983b96d917d076bc4db3313..130a245a77e68922fc84b0a9104a03d536dfe364 100644 (file)
--- a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
+++ b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts
@@ -93,6 +93,50 @@
        };
 
        soc {
+               pci@c0000000 {
+                       status = "ok";
+
+                       /*
+                        * In the boardfile for the Cambria from OpenWRT the interrupts
+                        * are assigned one per IDSEL, so all 4 interrupts from IDSEL
+                        * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2
+                        * connected to IRQ 10 etc. I find this highly unlikely so I
+                        * have instead assumed that they are rotated (swizzled) like
+                        * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
+                        */
+                       interrupt-map =
+                       /* IDSEL 1 */
+                       <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
+                       <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
+                       <0x0800 0 0 3 &gpio0 9  3>, /* INT C on slot 1 is irq 9 */
+                       <0x0800 0 0 4 &gpio0 8  3>, /* INT D on slot 1 is irq 8 */
+                       /* IDSEL 2 */
+                       <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
+                       <0x1000 0 0 2 &gpio0 9  3>, /* INT B on slot 2 is irq 9 */
+                       <0x1000 0 0 3 &gpio0 8  3>, /* INT C on slot 2 is irq 8 */
+                       <0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */
+                       /* IDSEL 3 */
+                       <0x1800 0 0 1 &gpio0 9  3>, /* INT A on slot 3 is irq 9 */
+                       <0x1800 0 0 2 &gpio0 8  3>, /* INT B on slot 3 is irq 8 */
+                       <0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */
+                       <0x1800 0 0 4 &gpio0 10 3>, /* INT D on slot 3 is irq 10 */
+                       /* IDSEL 4 */
+                       <0x2000 0 0 1 &gpio0 8  3>, /* INT A on slot 3 is irq 8 */
+                       <0x2000 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
+                       <0x2000 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
+                       <0x2000 0 0 4 &gpio0 9  3>, /* INT D on slot 3 is irq 9 */
+                       /* IDSEL 6 */
+                       <0x3000 0 0 1 &gpio0 10 3>, /* INT A on slot 3 is irq 10 */
+                       <0x3000 0 0 2 &gpio0 9  3>, /* INT B on slot 3 is irq 9 */
+                       <0x3000 0 0 3 &gpio0 8  3>, /* INT C on slot 3 is irq 8 */
+                       <0x3000 0 0 4 &gpio0 11 3>, /* INT D on slot 3 is irq 11 */
+                       /* IDSEL 15 */
+                       <0x7800 0 0 1 &gpio0 8  3>, /* INT A on slot 3 is irq 8 */
+                       <0x7800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
+                       <0x7800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
+                       <0x7800 0 0 4 &gpio0 9  3>; /* INT D on slot 3 is irq 9 */
+               };
+
                ethernet@c800a000 {
                        status = "ok";
                        queue-rx = <&qmgr 4>;

diff --git a/arch/arm/boot/dts/intel-ixp43x.dtsi b/arch/arm/boot/dts/intel-ixp43x.dtsi
index 494fb2ff57a0076d6c577bda12a38d64e702e357..1d0817c6e3f93be80b6c7e85a84151697f1ce9ff 100644 (file)
--- a/arch/arm/boot/dts/intel-ixp43x.dtsi
+++ b/arch/arm/boot/dts/intel-ixp43x.dtsi
@@ -8,6 +8,10 @@
 
 / {
        soc {
+               pci@c0000000 {
+                       compatible = "intel,ixp43x-pci";
+               };
+
                interrupt-controller@c8003000 {
                        compatible = "intel,ixp43x-interrupt";
                };

diff --git a/arch/arm/boot/dts/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel-ixp4xx.dtsi
index b3de0501cf6fc8c4c68936b2e20a5a26e17d67cd..edfd81d9f3dab0116df947e1bff3b75b4bca7045 100644 (file)
--- a/arch/arm/boot/dts/intel-ixp4xx.dtsi
+++ b/arch/arm/boot/dts/intel-ixp4xx.dtsi
@@ -20,6 +20,42 @@
                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               pci@c0000000 {
+                       /* compatible filled in by per-soc device tree */
+                       reg = <0xc0000000 0x1000>;
+                       interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
+                                    <9 IRQ_TYPE_LEVEL_HIGH>,
+                                    <10 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       bus-range = <0x00 0xff>;
+                       status = "disabled";
+
+                       ranges =
+                       /*
+                        * 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff
+                        * done in 4 chunks of 16MB each.
+                        */
+                       <0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
+                       /* 64KB I/O space at 0x4c000000 */
+                       <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
+
+                       /*
+                        * This needs to map to the start of physical memory so
+                        * PCI devices can see all (hopefully) memory. This is done
+                        * using 4 1:1 16MB windows, so the RAM should not be more than
+                        * 64 MB for this to work. If your memory is anywhere else
+                        * than at 0x0 you need to alter this.
+                        */
+                       dma-ranges =
+                       <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
+
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0xf800 0 0 7>;
+                       /* Each unique DTS using PCI must specify the swizzling */
+               };
+
                uart0: serial@c8000000 {
                        compatible = "intel,xscale-uart";
                        reg = <0xc8000000 0x1000>;