clk: samsung: Pass mask to wait_until_mux_stable()

Make it possible to use wait_until_mux_stable() for MUX registers where
the mask is different from MUX_MASK (e.g. in upcoming CPU clock
implementation for Exynos850).

No functional change.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240224202053.25313-12-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 237f6a8c52401e4524b819414ea97d480cc98e57..deb5e708f762d56139df97cd0961f79bae131890 100644 (file)
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -135,16 +135,16 @@ static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask)
  * value was changed.
  */
 static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
-                                 unsigned long mux_value)
+                                 unsigned long mask, unsigned long mux_value)
 {
        unsigned long timeout = jiffies + msecs_to_jiffies(MAX_STAB_TIME);
 
        do {
-               if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
+               if (((readl(mux_reg) >> mux_pos) & mask) == mux_value)
                        return;
        } while (time_before(jiffies, timeout));
 
-       if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
+       if (((readl(mux_reg) >> mux_pos) & mask) == mux_value)
                return;
 
        pr_err("%s: re-parenting mux timed-out\n", __func__);
@@ -249,7 +249,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
        /* select sclk_mpll as the alternate parent */
        mux_reg = readl(base + regs->mux_sel);
        writel(mux_reg | (1 << 16), base + regs->mux_sel);
-       wait_until_mux_stable(base + regs->mux_stat, 16, 2);
+       wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 2);
 
        /* alternate parent is active now. set the dividers */
        writel(div0, base + regs->div_cpu0);
@@ -290,7 +290,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
        /* select mout_apll as the alternate parent */
        mux_reg = readl(base + regs->mux_sel);
        writel(mux_reg & ~(1 << 16), base + regs->mux_sel);
-       wait_until_mux_stable(base + regs->mux_stat, 16, 1);
+       wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 1);
 
        if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
                div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
@@ -362,7 +362,7 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
        /* select the alternate parent */
        mux_reg = readl(base + regs->mux_sel);
        writel(mux_reg | 1, base + regs->mux_sel);
-       wait_until_mux_stable(base + regs->mux_stat, 0, 2);
+       wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 2);
 
        /* alternate parent is active now. set the dividers */
        writel(div0, base + regs->div_cpu0);
@@ -390,7 +390,7 @@ static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
        /* select apll as the alternate parent */
        mux_reg = readl(base + regs->mux_sel);
        writel(mux_reg & ~1, base + regs->mux_sel);
-       wait_until_mux_stable(base + regs->mux_stat, 0, 1);
+       wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 1);
 
        exynos_set_safe_div(cpuclk, div, div_mask);
        spin_unlock_irqrestore(cpuclk->lock, flags);