drm/amd/display: Switch to correct DTO on HDMI

[Why]
For Pixel Rate control, when on HDMI, HDMI DTO should be selected
instead of DP DTO.

[How]
Pass HDMI parameter for HDMI stream, and select correct DTO.

Signed-off-by: Chris Park <chris.park@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index c0989a04d025d598bcc8a931f594ec306058327f..5b87f937554d310341e35cdcb5d5d1345a6805b0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -323,6 +323,8 @@ static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
                                if (pipe_ctx->stream_res.audio != NULL)
                                        dto_params.req_audio_dtbclk_khz = 24000;
                        }
+                       if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
+                               dto_params.is_hdmi = true;
 
                        dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
                        //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
index 152a76ad7957b2d052a97fdb843a5db90348cd88..12fc3afd9acd41ac83b9ffb3d24e252b38f166f6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c
@@ -171,6 +171,9 @@ void dccg32_set_dtbclk_dto(
                REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst],
                                DTBCLK_DTO_ENABLE[params->otg_inst], 0,
                                PIPE_DTO_SRC_SEL[params->otg_inst], 1);
+               if (params->is_hdmi)
+                       REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
+                               PIPE_DTO_SRC_SEL[params->otg_inst], 0);
 
                REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0);
                REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0);
@@ -188,6 +191,7 @@ static void dccg32_set_valid_pixel_rate(
        dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
        dto_params.otg_inst = otg_inst;
        dto_params.pixclk_khz = pixclk_khz;
+       dto_params.is_hdmi = true;
 
        dccg32_set_dtbclk_dto(dccg, &dto_params);
 }