fpga: m10bmc-sec: expose max10 flash update count

Extend the MAX10 BMC Secure Update driver to provide a sysfs file to
expose the flash update count.

Reviewed-by: Tom Rix <trix@redhat.com>
Tested-by: Tianfei Zhang <tianfei.zhang@intel.com>
Signed-off-by: Russ Weight <russell.h.weight@intel.com>
Link: https://lore.kernel.org/r/20220606160038.846236-4-russell.h.weight@intel.com
Signed-off-by: Xu Yilun <yilun.xu@intel.com>

diff --git a/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update b/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update
index a208367e6956d9761bdf8beb1036b89e6b649298..6114e15885e5109df0406440e8350adbbdc1dcc3 100644 (file)
--- a/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update
+++ b/Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update
@@ -27,3 +27,11 @@ Description: Read only. Returns the root entry hash for the BMC image
                "hash not programmed".  This file is only visible if the
                underlying device supports it.
                Format: string.
+
+What:          /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/flash_count
+Date:          Sep 2022
+KernelVersion: 5.20
+Contact:       Russ Weight <russell.h.weight@intel.com>
+Description:   Read only. Returns number of times the secure update
+               staging area has been flashed.
+               Format: "%u".

diff --git a/drivers/fpga/intel-m10-bmc-sec-update.c b/drivers/fpga/intel-m10-bmc-sec-update.c
index f9f39d2cfe5be56c403784cbb6f31e4267146f78..25b21f11697652ced65113545432fbe17a0e523b 100644 (file)
--- a/drivers/fpga/intel-m10-bmc-sec-update.c
+++ b/drivers/fpga/intel-m10-bmc-sec-update.c
@@ -78,7 +78,50 @@ DEVICE_ATTR_SEC_REH_RO(bmc, BMC_PROG_MAGIC, BMC_PROG_ADDR, BMC_REH_ADDR);
 DEVICE_ATTR_SEC_REH_RO(sr, SR_PROG_MAGIC, SR_PROG_ADDR, SR_REH_ADDR);
 DEVICE_ATTR_SEC_REH_RO(pr, PR_PROG_MAGIC, PR_PROG_ADDR, PR_REH_ADDR);
 
+#define FLASH_COUNT_SIZE 4096  /* count stored as inverted bit vector */
+
+static ssize_t flash_count_show(struct device *dev,
+                               struct device_attribute *attr, char *buf)
+{
+       struct m10bmc_sec *sec = dev_get_drvdata(dev);
+       unsigned int stride, num_bits;
+       u8 *flash_buf;
+       int cnt, ret;
+
+       stride = regmap_get_reg_stride(sec->m10bmc->regmap);
+       num_bits = FLASH_COUNT_SIZE * 8;
+
+       flash_buf = kmalloc(FLASH_COUNT_SIZE, GFP_KERNEL);
+       if (!flash_buf)
+               return -ENOMEM;
+
+       if (FLASH_COUNT_SIZE % stride) {
+               dev_err(sec->dev,
+                       "FLASH_COUNT_SIZE (0x%x) not aligned to stride (0x%x)\n",
+                       FLASH_COUNT_SIZE, stride);
+               WARN_ON_ONCE(1);
+               return -EINVAL;
+       }
+
+       ret = regmap_bulk_read(sec->m10bmc->regmap, STAGING_FLASH_COUNT,
+                              flash_buf, FLASH_COUNT_SIZE / stride);
+       if (ret) {
+               dev_err(sec->dev,
+                       "failed to read flash count: %x cnt %x: %d\n",
+                       STAGING_FLASH_COUNT, FLASH_COUNT_SIZE / stride, ret);
+               goto exit_free;
+       }
+       cnt = num_bits - bitmap_weight((unsigned long *)flash_buf, num_bits);
+
+exit_free:
+       kfree(flash_buf);
+
+       return ret ? : sysfs_emit(buf, "%u\n", cnt);
+}
+static DEVICE_ATTR_RO(flash_count);
+
 static struct attribute *m10bmc_security_attrs[] = {
+       &dev_attr_flash_count.attr,
        &dev_attr_bmc_root_entry_hash.attr,
        &dev_attr_sr_root_entry_hash.attr,
        &dev_attr_pr_root_entry_hash.attr,