ARM: dts: socfpga: Add Google Chameleon v3 devicetree

Add devicetree for the Google Chameleon v3 board.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b0dccad58a1d7b80d236e7596812fe9d9ced79c1..c7b194115c5cf88dc61a68850ec47e8875023b7c 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1148,6 +1148,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
        s5pv210-torbreck.dtb
 dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
        socfpga_arria5_socdk.dtb \
+       socfpga_arria10_chameleonv3.dtb \
        socfpga_arria10_socdk_nand.dtb \
        socfpga_arria10_socdk_qspi.dtb \
        socfpga_arria10_socdk_sdmmc.dtb \

diff --git a/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts b/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts
new file mode 100644 (file)
index 0000000..422d00c
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_chameleonv3.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+#include "socfpga_arria10_mercury_aa1.dtsi"
+
+/ {
+       model = "Google Chameleon V3";
+       compatible = "google,chameleon-v3", "enclustra,mercury-aa1",
+                    "altr,socfpga-arria10", "altr,socfpga";
+
+       aliases {
+               serial0 = &uart0;
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+       };
+};
+
+&gmac0 {
+       status = "okay";
+};
+
+&gpio0 {
+       status = "okay";
+};
+
+&gpio1 {
+       status = "okay";
+};
+
+&gpio2 {
+       status = "okay";
+};
+
+&i2c0 {
+       status = "okay";
+
+       ssm2603: audio-codec@1a {
+               compatible = "adi,ssm2603";
+               reg = <0x1a>;
+       };
+};
+
+&i2c1 {
+       status = "okay";
+
+       u80: gpio@21 {
+               compatible = "nxp,pca9535";
+               reg = <0x21>;
+               gpio-controller;
+               #gpio-cells = <2>;
+
+               gpio-line-names =
+                       "SOM_AUD_MUTE",
+                       "DP1_OUT_CEC_EN",
+                       "DP2_OUT_CEC_EN",
+                       "DP1_SOM_PS8469_CAD",
+                       "DPD_SOM_PS8469_CAD",
+                       "DP_OUT_PWR_EN",
+                       "STM32_RST_L",
+                       "STM32_BOOT0",
+
+                       "FPGA_PROT",
+                       "STM32_FPGA_COMM0",
+                       "TP119",
+                       "TP120",
+                       "TP121",
+                       "TP122",
+                       "TP123",
+                       "TP124";
+       };
+};
+
+&mmc {
+       status = "okay";
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};
+
+&usb0 {
+       status = "okay";
+       dr_mode = "host";
+};