arm64: dts: juno: Add cache-level property to L2 caches
authorSudeep Holla <sudeep.holla@arm.com>
Wed, 29 Jun 2022 09:59:59 +0000 (10:59 +0100)
committerSudeep Holla <sudeep.holla@arm.com>
Wed, 29 Jun 2022 10:52:09 +0000 (11:52 +0100)
Add the missing cache-level property to L2 caches. This is needed if
we need to find the last level cache directly from the device tree cache
node.

Link: https://lore.kernel.org/r/20220629095959.1115587-1-sudeep.holla@arm.com
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
arch/arm64/boot/dts/arm/juno-r1.dts
arch/arm64/boot/dts/arm/juno-r2.dts
arch/arm64/boot/dts/arm/juno.dts

index f099fb611d4e5fa9ac7eb88cbcfd88c95aaa1131..6451c62146fdab52eb28292022d2f3d358e86c28 100644 (file)
                        cache-size = <0x200000>;
                        cache-line-size = <64>;
                        cache-sets = <2048>;
+                       cache-level = <2>;
                };
 
                A53_L2: l2-cache1 {
                        cache-size = <0x100000>;
                        cache-line-size = <64>;
                        cache-sets = <1024>;
+                       cache-level = <2>;
                };
        };
 
index 709389582ae370205deeef1436d0b271de91f042..438cd1ff4bd0809721942d69274ba09ac692925f 100644 (file)
                        cache-size = <0x200000>;
                        cache-line-size = <64>;
                        cache-sets = <2048>;
+                       cache-level = <2>;
                };
 
                A53_L2: l2-cache1 {
                        cache-size = <0x100000>;
                        cache-line-size = <64>;
                        cache-sets = <1024>;
+                       cache-level = <2>;
                };
        };
 
index dbc22e70b62c1cfda61d5d0c50bc842738dfa1d7..cf4a582113999f737f7a78094dd0df8cbc8b6a42 100644 (file)
                        cache-size = <0x200000>;
                        cache-line-size = <64>;
                        cache-sets = <2048>;
+                       cache-level = <2>;
                };
 
                A53_L2: l2-cache1 {
                        cache-size = <0x100000>;
                        cache-line-size = <64>;
                        cache-sets = <1024>;
+                       cache-level = <2>;
                };
        };