drm/amd/display: Allow Z8 when stutter threshold is not met for dcn35
authorBhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Thu, 14 Mar 2024 17:09:31 +0000 (13:09 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 27 Mar 2024 05:43:00 +0000 (01:43 -0400)
[Why&How]
Some panels don't meet the stutter threshold (4k etc), this leads to
power regressions. Allow z8 for panels that don't meet the threshold
but support PSR/replay

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c

index 33ea89f20449b94400860f2e792817d47e8163b2..714c2fe03c5f41defb458ada9b7c19ea3a1c1543 100644 (file)
@@ -603,7 +603,7 @@ void dcn35_decide_zstate_support(struct dc *dc, struct dc_state *context)
                if (is_pwrseq0 && allow_z10)
                        support = DCN_ZSTATE_SUPPORT_ALLOW;
                else if (is_pwrseq0 && (is_psr || is_replay))
-                       support = allow_z8 ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY : DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;
+                       support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY;
                else if (allow_z8)
                        support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY;
 
index 72cca367062e163be2dbe41f7af452c515467a54..e2489eaabb207dc3e44d61e837771d88a58b98da 100644 (file)
@@ -570,6 +570,7 @@ static bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_s
        struct dml2_dcn_clocks out_clks;
        unsigned int result = 0;
        bool need_recalculation = false;
+       uint32_t cstate_enter_plus_exit_z8_ns;
 
        if (!context || context->stream_count == 0)
                return true;
@@ -641,6 +642,14 @@ static bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_s
                dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.d, &dml2->v20.dml_core_ctx);
                //copy for deciding zstate use
                context->bw_ctx.dml.vba.StutterPeriod = context->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriod;
+
+               cstate_enter_plus_exit_z8_ns = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns;
+
+               if (context->bw_ctx.dml.vba.StutterPeriod < in_dc->debug.minimum_z8_residency_time &&
+                               cstate_enter_plus_exit_z8_ns < in_dc->debug.minimum_z8_residency_time * 1000)
+                       cstate_enter_plus_exit_z8_ns = in_dc->debug.minimum_z8_residency_time * 1000;
+
+               context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus_exit_z8_ns;
        }
 
        return result;