target/riscv: zvbb implies zvkb
authorJerry Zhang Jian <jerry.zhangjian@sifive.com>
Tue, 28 May 2024 13:03:49 +0000 (21:03 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 26 Jun 2024 12:30:52 +0000 (22:30 +1000)
According to RISC-V crypto spec, Zvkb extension is a
subset of the Zvbb extension [1].

1: https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10

Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240528130349.20193-1-jerry.zhangjian@sifive.com>
[ Changes by AF:
 - Tidy up commit message
 - Rebase
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/tcg/tcg-cpu.c

index 683f604d9f064b4b8d938982816ff920187297eb..fa8a17cc60d06043404df748574a4c93b0084b01 100644 (file)
@@ -667,6 +667,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
     }
 
+    if (cpu->cfg.ext_zvbb) {
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
+    }
+
     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
          cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
          cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {