pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro

Currently we assume all the port pins are sequential ie always PX_0 to
PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to
P28_5 which have holes in them, for example only one pin on port19 is
available and that is P19_1 and not P19_0. So to handle such cases
include pinmap for each port which would indicate the pin availability
on each port. As the pincount can be calculated based on pinmap drop this
from RZG2L_GPIO_PORT_PACK() macro.

Previously we had a max of 7 pins on each port but on RZ/Five Port-20
has 8 pins, so move the single pin configuration to BIT(63).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240129135556.63466-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 90fb67bc473f86e5fae993e55c729311fd2d85be..2b1a715c8a006f059298b97fb4ef3c668e3a68e0 100644 (file)
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -80,19 +80,20 @@
  * n indicates number of pins in the port, a is the register index
  * and f is pin configuration capabilities supported.
  */
-#define PIN_CFG_PIN_CNT_MASK           GENMASK(30, 28)
+#define PIN_CFG_PIN_MAP_MASK           GENMASK_ULL(35, 28)
 #define PIN_CFG_PIN_REG_MASK           GENMASK(27, 20)
 #define PIN_CFG_MASK                   GENMASK(19, 0)
-#define RZG2L_GPIO_PORT_PACK(n, a, f)  (FIELD_PREP_CONST(PIN_CFG_PIN_CNT_MASK, (n)) | \
+
+#define RZG2L_GPIO_PORT_PACK(n, a, f)  ((((1ULL << (n)) - 1) << 28) | \
                                         FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \
                                         FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
 
 /*
- * BIT(31) indicates dedicated pin, p is the register index while
+ * BIT(63) indicates dedicated pin, p is the register index while
  * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits
  * (b * 8) and f is the pin configuration capabilities supported.
  */
-#define RZG2L_SINGLE_PIN               BIT(31)
+#define RZG2L_SINGLE_PIN               BIT_ULL(63)
 #define RZG2L_SINGLE_PIN_INDEX_MASK    GENMASK(30, 24)
 #define RZG2L_SINGLE_PIN_BITS_MASK     GENMASK(22, 20)
 
@@ -195,12 +196,12 @@ struct rzg2l_hwcfg {
 
 struct rzg2l_dedicated_configs {
        const char *name;
-       u32 config;
+       u64 config;
 };
 
 struct rzg2l_pinctrl_data {
        const char * const *port_pins;
-       const u32 *port_pin_configs;
+       const u64 *port_pin_configs;
        unsigned int n_ports;
        const struct rzg2l_dedicated_configs *dedicated_pins;
        unsigned int n_port_pins;
@@ -301,7 +302,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
        pins = group->grp.pins;
 
        for (i = 0; i < group->grp.npins; i++) {
-               unsigned int *pin_data = pctrl->desc.pins[pins[i]].drv_data;
+               u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data;
                u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
                u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]);
 
@@ -564,13 +565,13 @@ done:
 }
 
 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
-                                  u32 cfg, u32 port, u8 bit)
+                                  u64 cfg, u32 port, u8 bit)
 {
-       u8 pincount = FIELD_GET(PIN_CFG_PIN_CNT_MASK, cfg);
+       u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);
        u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
-       u32 data;
+       u64 data;
 
-       if (bit >= pincount || port >= pctrl->data->n_port_pins)
+       if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins)
                return -EINVAL;
 
        data = pctrl->data->port_pin_configs[port];
@@ -862,7 +863,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
        enum pin_config_param param = pinconf_to_config_param(*config);
        const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
        const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
-       unsigned int *pin_data = pin->drv_data;
+       u64 *pin_data = pin->drv_data;
        unsigned int arg = 0;
        u32 off, cfg;
        int ret;
@@ -965,7 +966,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
        const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
        const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
        struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin];
-       unsigned int *pin_data = pin->drv_data;
+       u64 *pin_data = pin->drv_data;
        enum pin_config_param param;
        unsigned int i, arg, index;
        u32 cfg, off;
@@ -1170,7 +1171,7 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
 {
        struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
        const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
-       u32 *pin_data = pin_desc->drv_data;
+       u64 *pin_data = pin_desc->drv_data;
        u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
        u32 port = RZG2L_PIN_ID_TO_PORT(offset);
        u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
@@ -1202,7 +1203,7 @@ static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset,
                                     bool output)
 {
        const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
-       unsigned int *pin_data = pin_desc->drv_data;
+       u64 *pin_data = pin_desc->drv_data;
        u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
        u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
        unsigned long flags;
@@ -1223,7 +1224,7 @@ static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 {
        struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
        const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
-       unsigned int *pin_data = pin_desc->drv_data;
+       u64 *pin_data = pin_desc->drv_data;
        u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
        u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
 
@@ -1254,7 +1255,7 @@ static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,
 {
        struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
        const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
-       unsigned int *pin_data = pin_desc->drv_data;
+       u64 *pin_data = pin_desc->drv_data;
        u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
        u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
        unsigned long flags;
@@ -1287,7 +1288,7 @@ static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset)
 {
        struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
        const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
-       unsigned int *pin_data = pin_desc->drv_data;
+       u64 *pin_data = pin_desc->drv_data;
        u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
        u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
        u16 reg16;
@@ -1372,7 +1373,7 @@ static const char * const rzg2l_gpio_names[] = {
        "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7",
 };
 
-static const u32 r9a07g044_gpio_configs[] = {
+static const u64 r9a07g044_gpio_configs[] = {
        RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS),
        RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS),
        RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS),
@@ -1424,7 +1425,7 @@ static const u32 r9a07g044_gpio_configs[] = {
        RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
 };
 
-static const u32 r9a07g043_gpio_configs[] = {
+static const u64 r9a07g043_gpio_configs[] = {
        RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
        RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
        RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
@@ -1446,7 +1447,7 @@ static const u32 r9a07g043_gpio_configs[] = {
        RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
 };
 
-static const u32 r9a08g045_gpio_configs[] = {
+static const u64 r9a08g045_gpio_configs[] = {
        RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)),                        /* P0  */
        RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
                                                                PIN_CFG_IO_VMC_ETH0)) |
@@ -1614,12 +1615,12 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_
        bit = virq % 8;
 
        if (port >= data->n_ports ||
-           bit >= FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[port]))
+           bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port])))
                return -EINVAL;
 
        gpioint = bit;
        for (i = 0; i < port; i++)
-               gpioint += FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[i]);
+               gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i]));
 
        return gpioint;
 }
@@ -1630,7 +1631,7 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d)
        struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
        unsigned int hwirq = irqd_to_hwirq(d);
        const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq];
-       unsigned int *pin_data = pin_desc->drv_data;
+       u64 *pin_data = pin_desc->drv_data;
        u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
        u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq);
        unsigned long flags;
@@ -1657,7 +1658,7 @@ static void rzg2l_gpio_irq_enable(struct irq_data *d)
        struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
        unsigned int hwirq = irqd_to_hwirq(d);
        const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq];
-       unsigned int *pin_data = pin_desc->drv_data;
+       u64 *pin_data = pin_desc->drv_data;
        u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
        u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq);
        unsigned long flags;
@@ -1794,7 +1795,8 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc,
                bit = offset % 8;
 
                if (port >= pctrl->data->n_ports ||
-                   bit >= FIELD_GET(PIN_CFG_PIN_CNT_MASK, pctrl->data->port_pin_configs[port]))
+                   bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK,
+                                             pctrl->data->port_pin_configs[port])))
                        clear_bit(offset, valid_mask);
        }
 }
@@ -1876,7 +1878,7 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
        const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
        struct pinctrl_pin_desc *pins;
        unsigned int i, j;
-       u32 *pin_data;
+       u64 *pin_data;
        int ret;
 
        pctrl->desc.name = DRV_NAME;