fdt_start = fw_getenvl("fdt_start");
        if (fdt_start)
                __dt_setup_arch((void *)KSEG0ADDR(fdt_start));
-       else if (fw_arg0 == -2)
-               __dt_setup_arch((void *)KSEG0ADDR(fw_arg1));
+       else if (fw_passed_dtb)
+               __dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb));
 
        if (mips_machtype != ATH79_MACH_GENERIC_OF) {
                ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 
        /* intended to somewhat resemble ARM; see Documentation/arm/Booting */
        if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
                dtb = phys_to_virt(fw_arg2);
-       else if (fw_arg0 == -2) /* UHI interface */
-               dtb = (void *)fw_arg1;
+       else if (fw_passed_dtb) /* UHI interface */
+               dtb = (void *)fw_passed_dtb;
        else if (__dtb_start != __dtb_end)
                dtb = (void *)__dtb_start;
        else
 
  */
 extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
 
+#ifdef CONFIG_USE_OF
+extern unsigned long fw_passed_dtb;
+#endif
+
 /*
  * Platform memory detection hook called by setup_arch
  */
 
        jr      t0
 0:
 
+#ifdef CONFIG_USE_OF
 #ifdef CONFIG_MIPS_RAW_APPENDED_DTB
-       PTR_LA          t0, __appended_dtb
+       PTR_LA          t2, __appended_dtb
 
 #ifdef CONFIG_CPU_BIG_ENDIAN
        li              t1, 0xd00dfeed
 #else
        li              t1, 0xedfe0dd0
 #endif
-       lw              t2, (t0)
-       bne             t1, t2, not_found
-        nop
+       lw              t0, (t2)
+       beq             t0, t1, dtb_found
+#endif
+       li              t1, -2
+       beq             a0, t1, dtb_found
+       move            t2, a1
 
-       move            a1, t0
-       PTR_LI          a0, -2
-not_found:
+       li              t2, 0
+dtb_found:
 #endif
        PTR_LA          t0, __bss_start         # clear .bss
        LONG_S          zero, (t0)
        LONG_S          a2, fw_arg2
        LONG_S          a3, fw_arg3
 
+#ifdef CONFIG_USE_OF
+       LONG_S          t2, fw_passed_dtb
+#endif
+
        MTC0            zero, CP0_CONTEXT       # clear context register
        PTR_LA          $28, init_thread_union
        /* Set the SP after an empty pt_regs.  */
 
 unsigned long kernelsp[NR_CPUS];
 unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
 
+#ifdef CONFIG_USE_OF
+unsigned long fw_passed_dtb;
+#endif
+
 #ifdef CONFIG_DEBUG_FS
 struct dentry *mips_debugfs_dir;
 static int __init debugfs_mips(void)
 
 
        set_io_port_base((unsigned long) KSEG1);
 
-       if (fw_arg0 == -2) /* UHI interface */
-               dtb = (void *)fw_arg1;
+       if (fw_passed_dtb) /* UHI interface */
+               dtb = (void *)fw_passed_dtb;
        else if (__dtb_start != __dtb_end)
                dtb = (void *)__dtb_start;
        else
 
 {
        ulong ftaddr = 0;
 
-       if ((fw_arg0 == -2) && fw_arg1 && !fw_arg2 && !fw_arg3)
-               return (ulong)fw_arg1;
+       if (fw_passed_dtb && !fw_arg2 && !fw_arg3)
+               return (ulong)fw_passed_dtb;
 
        if (__dtb_start < __dtb_end)
                ftaddr = (ulong)__dtb_start;