MIPS: mm: XBurst CPU requires sync after DMA

I am not sure why this is required, but if this is not enabled, reading
from a buffer in which data has been DMA'd may read incorrect values.

This used to happen for instance in mmc_app_send_scr()
(drivers/mmc/core/sd_ops.c), where data is DMA'd to a buffer then copied
by the CPU to a different location.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index baa4ea9a0f25ac61b111143960dba3e5b8ecef68..7badc40baa1f4291d6a432b67c0f393c9a69c3ad 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -112,6 +112,7 @@ config MACH_INGENIC
        select SYS_SUPPORTS_LITTLE_ENDIAN
        select SYS_SUPPORTS_ZBOOT
        select DMA_NONCOHERENT
+       select ARCH_HAS_SYNC_DMA_FOR_CPU
        select IRQ_MIPS_CPU
        select PINCTRL
        select GPIOLIB

diff --git a/arch/mips/mm/dma-noncoherent.c b/arch/mips/mm/dma-noncoherent.c
index 212f3ce75a6bd393145a28a4061264209883b58d..3c4fc97b9f394b0c2f2d22c5f59d23c0105cbfb3 100644 (file)
--- a/arch/mips/mm/dma-noncoherent.c
+++ b/arch/mips/mm/dma-noncoherent.c
@@ -32,6 +32,7 @@ static inline bool cpu_needs_post_dma_flush(void)
        case CPU_R12000:
        case CPU_BMIPS5000:
        case CPU_LOONGSON2EF:
+       case CPU_XBURST:
                return true;
        default:
                /*