}
 }
 
+static int bnxt_alloc_rss_indir_tbl(struct bnxt *bp)
+{
+       int entries;
+
+       if (bp->flags & BNXT_FLAG_CHIP_P5)
+               entries = BNXT_MAX_RSS_TABLE_ENTRIES_P5;
+       else
+               entries = HW_HASH_INDEX_SIZE;
+
+       bp->rss_indir_tbl_entries = entries;
+       bp->rss_indir_tbl = kmalloc_array(entries, sizeof(*bp->rss_indir_tbl),
+                                         GFP_KERNEL);
+       if (!bp->rss_indir_tbl)
+               return -ENOMEM;
+       return 0;
+}
+
+static void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp)
+{
+       u16 max_rings, max_entries, pad, i;
+
+       if (!bp->rx_nr_rings)
+               return;
+
+       if (BNXT_CHIP_TYPE_NITRO_A0(bp))
+               max_rings = bp->rx_nr_rings - 1;
+       else
+               max_rings = bp->rx_nr_rings;
+
+       max_entries = bnxt_get_rxfh_indir_size(bp->dev);
+
+       for (i = 0; i < max_entries; i++)
+               bp->rss_indir_tbl[i] = ethtool_rxfh_indir_default(i, max_rings);
+
+       pad = bp->rss_indir_tbl_entries - max_entries;
+       if (pad)
+               memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16));
+}
+
 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
 {
        u32 i, j, max_rings;
        bnxt_free_ctx_mem(bp);
        kfree(bp->ctx);
        bp->ctx = NULL;
+       kfree(bp->rss_indir_tbl);
+       bp->rss_indir_tbl = NULL;
        bnxt_free_port_stats(bp);
        free_netdev(dev);
 }
         */
        bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
 
+       rc = bnxt_alloc_rss_indir_tbl(bp);
+       if (rc)
+               goto init_err_pci_clean;
+       bnxt_set_dflt_rss_indir_tbl(bp);
+
        if (BNXT_PF(bp)) {
                if (!bnxt_pf_wq) {
                        bnxt_pf_wq =
        bnxt_free_ctx_mem(bp);
        kfree(bp->ctx);
        bp->ctx = NULL;
+       kfree(bp->rss_indir_tbl);
+       bp->rss_indir_tbl = NULL;
 
 init_err_free:
        free_netdev(dev);
 
 #define BNXT_RSS_TABLE_MAX_TBL_P5      8
 #define BNXT_MAX_RSS_TABLE_SIZE_P5                             \
        (BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
+#define BNXT_MAX_RSS_TABLE_ENTRIES_P5                          \
+       (BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
 
        u32             rx_mask;
 
        struct bnxt_ring_grp_info       *grp_info;
        struct bnxt_vnic_info   *vnic_info;
        int                     nr_vnics;
+       u16                     *rss_indir_tbl;
+       u16                     rss_indir_tbl_entries;
        u32                     rss_hash_cfg;
 
        u16                     max_mtu;