drm/amd/display: Expand kernel doc for DC

This commit adds extra documentation for elements related to FAMs.

Tested-by: Mark Broadworth <mark.broadworth@amd.com>
Reviewed-by: Aurabindo Pillai <Aurabindo.Pillai@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 3450aca538b5837aaef8d472f6bc16d5b97a5d62..44f8db1605200ef314d1661c694a13124f7ef466 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -494,9 +494,12 @@ enum dcn_zstate_support_state {
        DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
        DCN_ZSTATE_SUPPORT_DISALLOW,
 };
-/*
- * For any clocks that may differ per pipe
- * only the max is stored in this structure
+
+/**
+ * dc_clocks - DC pipe clocks
+ *
+ * For any clocks that may differ per pipe only the max is stored in this
+ * structure
  */
 struct dc_clocks {
        int dispclk_khz;
@@ -523,6 +526,16 @@ struct dc_clocks {
        bool prev_p_state_change_support;
        bool fclk_prev_p_state_change_support;
        int num_ways;
+
+       /**
+        * @fw_based_mclk_switching
+        *
+        * DC has a mechanism that leverage the variable refresh rate to switch
+        * memory clock in cases that we have a large latency to achieve the
+        * memory clock change and a short vblank window. DC has some
+        * requirements to enable this feature, and this field describes if the
+        * system support or not such a feature.
+        */
        bool fw_based_mclk_switching;
        bool fw_based_mclk_switching_shut_down;
        int prev_num_ways;

diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 4d30ae0ca721a68b653817a7843cdc23a4d44786..f4dfd3a49b68ed163f04ba200234142ce846e7f6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -201,7 +201,18 @@ struct dc_stream_state {
        bool use_vsc_sdp_for_colorimetry;
        bool ignore_msa_timing_param;
 
+       /**
+        * @allow_freesync:
+        *
+        * It say if Freesync is enabled or not.
+        */
        bool allow_freesync;
+
+       /**
+        * @vrr_active_variable:
+        *
+        * It describes if VRR is in use.
+        */
        bool vrr_active_variable;
        bool freesync_on_desktop;
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dc_features.h b/drivers/gpu/drm/amd/display/dc/dml/dc_features.h
index 74e86732e30103fbeb557f5f8e7a8f2ac84ade90..2cbdd75429ffd6bc2f872e0004a5c9ba0a70bac7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dc_features.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dc_features.h
@@ -29,6 +29,13 @@
 #define DC__PRESENT 1
 #define DC__PRESENT__1 1
 #define DC__NUM_DPP 4
+
+/**
+ * @DC__VOLTAGE_STATES:
+ *
+ * Define the maximum amount of states supported by the ASIC. Every ASIC has a
+ * specific number of states; this macro defines the maximum number of states.
+ */
 #define DC__VOLTAGE_STATES 20
 #define DC__NUM_DPP__4 1
 #define DC__NUM_DPP__0_PRESENT 1

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
index f394b3f3922a8b4e9e3bd1de5bdc7242b8459a49..0bffae95f3a297e9b8398e46ed960b6ebec25fb8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
@@ -105,14 +105,39 @@ enum source_macro_tile_size {
 enum cursor_bpp {
        dm_cur_2bit = 0, dm_cur_32bit = 1, dm_cur_64bit = 2
 };
+
+/**
+ * @enum clock_change_support - It represents possible reasons to change the DRAM clock.
+ *
+ * DC may change the DRAM clock during its execution, and this enum tracks all
+ * the available methods. Note that every ASIC has their specific way to deal
+ * with these clock switch.
+ */
 enum clock_change_support {
+       /**
+        * @dm_dram_clock_change_uninitialized: If you see this, we might have
+        * a code initialization issue
+        */
        dm_dram_clock_change_uninitialized = 0,
+
+       /**
+        * @dm_dram_clock_change_vactive: Support DRAM switch in VActive
+        */
        dm_dram_clock_change_vactive,
+
+       /**
+        * @dm_dram_clock_change_vblank: Support DRAM switch in VBlank
+        */
        dm_dram_clock_change_vblank,
+
        dm_dram_clock_change_vactive_w_mall_full_frame,
        dm_dram_clock_change_vactive_w_mall_sub_vp,
        dm_dram_clock_change_vblank_w_mall_full_frame,
        dm_dram_clock_change_vblank_w_mall_sub_vp,
+
+       /**
+        * @dm_dram_clock_change_unsupported: Do not support DRAM switch
+        */
        dm_dram_clock_change_unsupported
 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 630f3395e90a087ff454384b391b4fa31390f04e..d46aa4817e7093b629255bfd7f2a15b93aeba059 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -419,6 +419,15 @@ struct vba_vars_st {
        double MinPixelChunkSizeBytes;
        unsigned int DCCMetaBufferSizeBytes;
        // Pipe/Plane Parameters
+
+       /** @VoltageLevel:
+        * Every ASIC has a fixed number of DPM states, and some devices might
+        * have some particular voltage configuration that does not map
+        * directly to the DPM states. This field tells how many states the
+        * target device supports; even though this field combines the DPM and
+        * special SOC voltages, it mostly matches the total number of DPM
+        * states.
+        */
        int VoltageLevel;
        double FabricClock;
        double DRAMSpeed;

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 9498105c98ab39a35063ec4b23f256888b681196..295845d49cb920825dbb55285b36af628f62edcf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -115,6 +115,13 @@ struct resource_funcs {
                                int vlevel);
        void (*update_soc_for_wm_a)(
                                struct dc *dc, struct dc_state *context);
+
+       /**
+        * @populate_dml_pipes - Populate pipe data struct
+        *
+        * Returns:
+        * Total of pipes available in the specific ASIC.
+        */
        int (*populate_dml_pipes)(
                struct dc *dc,
                struct dc_state *context,

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index cd2be729846b4684beab93c3e7aeca0db0cc2495..a819f0f97c5f3a0ffa562dfd5cd5da6aa178e0ec 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -35,6 +35,13 @@
  ******************************************************************************/
 
 #define MAX_AUDIOS 7
+
+/**
+ * @MAX_PIPES:
+ *
+ * Every ASIC support a fixed number of pipes; MAX_PIPES defines a large number
+ * to be used inside loops and for determining array sizes.
+ */
 #define MAX_PIPES 6
 #define MAX_DIG_LINK_ENCODERS 7
 #define MAX_DWB_PIPES  1