staging: r8188eu: AntCombination is always 2

AntCombination is initialized with 2 and never changed. Remove
resulting dead code.

Acked-by: Michael Straube <straube.linux@gmail.com>
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Link: https://lore.kernel.org/r/20211205151251.6861-11-martin@kaiser.cx
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/r8188eu/hal/odm_RTL8188E.c b/drivers/staging/r8188eu/hal/odm_RTL8188E.c
index e7a765f375d66820131dfec3ac13ad01b3f73e88..837e5a850264418290e24eb439cb4eb45a970985 100644 (file)
--- a/drivers/staging/r8188eu/hal/odm_RTL8188E.c
+++ b/drivers/staging/r8188eu/hal/odm_RTL8188E.c
@@ -58,7 +58,6 @@ static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm)
 {
        u32     value32, i;
        struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
-       u32     AntCombination = 2;
 
        for (i = 0; i < 6; i++) {
                dm_fat_tbl->Bssid[i] = 0;
@@ -85,36 +84,12 @@ static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm)
        ODM_SetBBReg(dm_odm, 0xb2c, BIT(31), 1);        /* Regb2c[31]=1'b1      output at CG only */
        ODM_SetBBReg(dm_odm, 0xca4, bMaskDWord, 0x000000a0);
 
-       /* antenna mapping table */
-       if (AntCombination == 2) {
-               if (!dm_odm->bIsMPChip) { /* testchip */
-                       ODM_SetBBReg(dm_odm, 0x858, BIT(10) | BIT(9) | BIT(8), 1);      /* Reg858[10:8]=3'b001 */
-                       ODM_SetBBReg(dm_odm, 0x858, BIT(13) | BIT(12) | BIT(11), 2);    /* Reg858[13:11]=3'b010 */
-               } else { /* MPchip */
-                       ODM_SetBBReg(dm_odm, 0x914, bMaskByte0, 1);
-                       ODM_SetBBReg(dm_odm, 0x914, bMaskByte1, 2);
-               }
-       } else if (AntCombination == 7) {
-               if (!dm_odm->bIsMPChip) { /* testchip */
-                       ODM_SetBBReg(dm_odm, 0x858, BIT(10) | BIT(9) | BIT(8), 0);      /* Reg858[10:8]=3'b000 */
-                       ODM_SetBBReg(dm_odm, 0x858, BIT(13) | BIT(12) | BIT(11), 1);    /* Reg858[13:11]=3'b001 */
-                       ODM_SetBBReg(dm_odm, 0x878, BIT(16), 0);
-                       ODM_SetBBReg(dm_odm, 0x858, BIT(15) | BIT(14), 2);      /* Reg878[0],Reg858[14:15])=3'b010 */
-                       ODM_SetBBReg(dm_odm, 0x878, BIT(19) | BIT(18) | BIT(17), 3);/* Reg878[3:1]=3b'011 */
-                       ODM_SetBBReg(dm_odm, 0x878, BIT(22) | BIT(21) | BIT(20), 4);/* Reg878[6:4]=3b'100 */
-                       ODM_SetBBReg(dm_odm, 0x878, BIT(25) | BIT(24) | BIT(23), 5);/* Reg878[9:7]=3b'101 */
-                       ODM_SetBBReg(dm_odm, 0x878, BIT(28) | BIT(27) | BIT(26), 6);/* Reg878[12:10]=3b'110 */
-                       ODM_SetBBReg(dm_odm, 0x878, BIT(31) | BIT(30) | BIT(29), 7);/* Reg878[15:13]=3b'111 */
-               } else { /* MPchip */
-                       ODM_SetBBReg(dm_odm, 0x914, bMaskByte0, 0);
-                       ODM_SetBBReg(dm_odm, 0x914, bMaskByte1, 1);
-                       ODM_SetBBReg(dm_odm, 0x914, bMaskByte2, 2);
-                       ODM_SetBBReg(dm_odm, 0x914, bMaskByte3, 3);
-                       ODM_SetBBReg(dm_odm, 0x918, bMaskByte0, 4);
-                       ODM_SetBBReg(dm_odm, 0x918, bMaskByte1, 5);
-                       ODM_SetBBReg(dm_odm, 0x918, bMaskByte2, 6);
-                       ODM_SetBBReg(dm_odm, 0x918, bMaskByte3, 7);
-               }
+       if (!dm_odm->bIsMPChip) { /* testchip */
+               ODM_SetBBReg(dm_odm, 0x858, BIT(10) | BIT(9) | BIT(8), 1);      /* Reg858[10:8]=3'b001 */
+               ODM_SetBBReg(dm_odm, 0x858, BIT(13) | BIT(12) | BIT(11), 2);    /* Reg858[13:11]=3'b010 */
+       } else { /* MPchip */
+               ODM_SetBBReg(dm_odm, 0x914, bMaskByte0, 1);
+               ODM_SetBBReg(dm_odm, 0x914, bMaskByte1, 2);
        }
 
        /* Default Ant Setting when no fast training */
@@ -122,8 +97,8 @@ static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm)
        ODM_SetBBReg(dm_odm, 0x864, BIT(5) | BIT(4) | BIT(3), 0);       /* Default RX */
        ODM_SetBBReg(dm_odm, 0x864, BIT(8) | BIT(7) | BIT(6), 1);       /* Optional RX */
 
-       /* Enter Traing state */
-       ODM_SetBBReg(dm_odm, 0x864, BIT(2) | BIT(1) | BIT(0), (AntCombination - 1));    /* Reg864[2:0]=3'd6     ant combination=reg864[2:0]+1 */
+       /* Enter Training state */
+       ODM_SetBBReg(dm_odm, 0x864, BIT(2) | BIT(1) | BIT(0), 1);
        ODM_SetBBReg(dm_odm, 0xc50, BIT(7), 1); /* RegC50[7]=1'b1               enable HW AntDiv */
 }