The doc [1] doesn't define the endianness, but the kernel driver
uses readl() to access the registers, so we can guess it depends
on the architecture endianness.
As riscv architecture endianness is little it might not change anything
for it.
Moreover, android implementation uses DEVICE_NATIVE_ENDIAN [2]
[1] https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT
[2] https://android.googlesource.com/platform/external/qemu/+/refs/heads/emu-master-dev/hw/timer/goldfish_timer.c#177
Fixes: 9a5b40b84279 ("hw: rtc: Add Goldfish RTC device")
Cc: Anup.Patel@wdc.com
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <
20201009113843.60995-2-lvivier@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
static const MemoryRegionOps goldfish_rtc_ops = {
.read = goldfish_rtc_read,
.write = goldfish_rtc_write,
- .endianness = DEVICE_LITTLE_ENDIAN,
+ .endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4