arm64: dts: allwinner: a64: Add MIPI DSI pipeline

Add MIPI DSI pipeline for Allwinner A64.

- dsi node, with A64 compatible since it doesn't support
  DSI_SCLK gating unlike A33
- dphy node, with A64 compatible with A33 fallback since
  DPHY on A64 and A33 is similar
- finally, attach the dsi_in to tcon0 for complete MIPI DSI

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Merlijn Wajer <merlijn@wizzup.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 9a89324d02dbf66645d7a3376cf1cb25dc1e55ee..92688b89c2a436653f4441d3c918efba4e3c6b89 100644 (file)
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -367,6 +367,12 @@
                                        #address-cells = <1>;
                                        #size-cells = <0>;
                                        reg = <1>;
+
+                                       tcon0_out_dsi: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&dsi_in_tcon0>;
+                                               allwinner,tcon-channel = <1>;
+                                       };
                                };
                        };
                };
@@ -1017,6 +1023,37 @@
                        status = "disabled";
                };
 
+               dsi: dsi@1ca0000 {
+                       compatible = "allwinner,sun50i-a64-mipi-dsi";
+                       reg = <0x01ca0000 0x1000>;
+                       interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_MIPI_DSI>;
+                       resets = <&ccu RST_BUS_MIPI_DSI>;
+                       phys = <&dphy>;
+                       phy-names = "dphy";
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port {
+                               dsi_in_tcon0: endpoint {
+                                       remote-endpoint = <&tcon0_out_dsi>;
+                               };
+                       };
+               };
+
+               dphy: d-phy@1ca1000 {
+                       compatible = "allwinner,sun50i-a64-mipi-dphy",
+                                    "allwinner,sun6i-a31-mipi-dphy";
+                       reg = <0x01ca1000 0x1000>;
+                       clocks = <&ccu CLK_BUS_MIPI_DSI>,
+                                <&ccu CLK_DSI_DPHY>;
+                       clock-names = "bus", "mod";
+                       resets = <&ccu RST_BUS_MIPI_DSI>;
+                       status = "disabled";
+                       #phy-cells = <0>;
+               };
+
                hdmi: hdmi@1ee0000 {
                        compatible = "allwinner,sun50i-a64-dw-hdmi",
                                     "allwinner,sun8i-a83t-dw-hdmi";