ARM: tegra: nexus7: Use PLLC for WiFi MMC clock parent

The default parent for all MMCs is PLLP, which is running at 408 MHz on
Tegra30 and 50 MHz clock can't be derived from PLLP. The maximum SDIO
clock rate is 50 MHz, but this rate isn't achievable using PLLP.

Let's switch the WiFi MMC clock parent to PLLC in order to get true 50
MHz. This patch doesn't fix any problems, it's just a minor improvement.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
index 9999e1afd4654ff0490e093a8ea1e01d22cabf42..bca77ee33c74e775f94f80dc68b1c8774068e26b 100644 (file)
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
@@ -945,6 +945,11 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
+               assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
+               assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
+               assigned-clock-rates = <50000000>;
+
+               max-frequency = <50000000>;
                keep-power-in-suspend;
                bus-width = <4>;
                non-removable;