ARM: dts: Group omap3 CM_CLKSEL1_PLL clocks
authorTony Lindgren <tony@atomide.com>
Fri, 29 Apr 2022 06:57:36 +0000 (09:57 +0300)
committerTony Lindgren <tony@atomide.com>
Tue, 3 May 2022 06:15:43 +0000 (09:15 +0300)
The clksel related registers on omap3 cause unique_unit_address and
node_name_chars_strict warnings with the W=1 or W=2 make flags enabled.

With the clock drivers updated, we can now avoid most of these warnings
by grouping the TI component clocks using the TI clksel binding, and
with the use of clock-output-names property to avoid non-standard node
names for the clocks.

Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/boot/dts/omap3xxx-clocks.dtsi

index 80e63f185427e3c50164427238f740a4bc365b29..d101f0a40502a090769c0df0b6e494c9e452f0f6 100644 (file)
                clock-frequency = <0x0>;
        };
 
-       dpll3_m2_ck: dpll3_m2_ck@d40 {
-               #clock-cells = <0>;
-               compatible = "ti,divider-clock";
-               clocks = <&dpll3_ck>;
-               ti,bit-shift = <27>;
-               ti,max-div = <31>;
-               reg = <0x0d40>;
-               ti,index-starts-at-one;
-       };
-
        core_ck: core_ck {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clock-div = <1>;
        };
 
-       omap_96m_fck: omap_96m_fck@d40 {
-               #clock-cells = <0>;
-               compatible = "ti,mux-clock";
-               clocks = <&cm_96m_fck>, <&sys_ck>;
-               ti,bit-shift = <6>;
-               reg = <0x0d40>;
+       /* CM_CLKSEL1_PLL */
+       clock@d40 {
+               compatible = "ti,clksel";
+               reg = <0xd40>;
+               #clock-cells = <2>;
+               #address-cells = <0>;
+
+               dpll3_m2_ck: clock-dpll3-m2 {
+                       #clock-cells = <0>;
+                       compatible = "ti,divider-clock";
+                       clock-output-names = "dpll3_m2_ck";
+                       clocks = <&dpll3_ck>;
+                       ti,bit-shift = <27>;
+                       ti,max-div = <31>;
+                       ti,index-starts-at-one;
+               };
+
+               omap_96m_fck: clock-omap-96m-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,mux-clock";
+                       clock-output-names = "omap_96m_fck";
+                       clocks = <&cm_96m_fck>, <&sys_ck>;
+                       ti,bit-shift = <6>;
+               };
+
+               omap_54m_fck: clock-omap-54m-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,mux-clock";
+                       clock-output-names = "omap_54m_fck";
+                       clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
+                       ti,bit-shift = <5>;
+               };
+
+               omap_48m_fck: clock-omap-48m-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,mux-clock";
+                       clock-output-names = "omap_48m_fck";
+                       clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
+                       ti,bit-shift = <3>;
+               };
        };
 
        dpll4_m3_ck: dpll4_m3_ck@e40 {
                ti,set-bit-to-disable;
        };
 
-       omap_54m_fck: omap_54m_fck@d40 {
-               #clock-cells = <0>;
-               compatible = "ti,mux-clock";
-               clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
-               ti,bit-shift = <5>;
-               reg = <0x0d40>;
-       };
-
        cm_96m_d2_fck: cm_96m_d2_fck {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
                clock-div = <2>;
        };
 
-       omap_48m_fck: omap_48m_fck@d40 {
-               #clock-cells = <0>;
-               compatible = "ti,mux-clock";
-               clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
-               ti,bit-shift = <3>;
-               reg = <0x0d40>;
-       };
-
        omap_12m_fck: omap_12m_fck {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";