PCI: qcom: Add missing macros for register fields

Some of the registers are changed using hardcoded bitfields without macros.
This provides no information on what the register setting is about. So add
the macros to those fields for making the code more understandable.

Link: https://lore.kernel.org/r/20230316081117.14288-6-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 44c31c65695ad25a82cd8c76c71063719dbe5189..f48990ac86ddb51b57e70d65da15d3b35f290712 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -63,6 +63,7 @@
 #define MISC_CONTROL_1_REG                     0x8BC
 
 /* PARF_SYS_CTRL register fields */
+#define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN       BIT(29)
 #define MST_WAKEUP_EN                          BIT(13)
 #define SLV_WAKEUP_EN                          BIT(12)
 #define MSTR_ACLK_CGC_DIS                      BIT(10)
@@ -87,6 +88,7 @@
 /* PARF_PHY_CTRL register fields */
 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK      GENMASK(20, 16)
 #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x)                FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x)
+#define PHY_TEST_PWR_DOWN                      BIT(0)
 
 /* PARF_PHY_REFCLK register fields */
 #define PHY_REFCLK_SSP_EN                      BIT(16)
@@ -103,6 +105,12 @@
 #define MSTR_AXI_CLK_EN                                BIT(1)
 #define BYPASS                                 BIT(4)
 
+/* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
+#define EN                                     BIT(31)
+
+/* PARF_LTSSM register fields */
+#define LTSSM_EN                               BIT(8)
+
 /* PARF_DEVICE_TYPE register fields */
 #define DEVICE_TYPE_RC                         0x4
 
@@ -440,7 +448,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie)
 
        /* enable PCIe clocks and resets */
        val = readl(pcie->parf + PARF_PHY_CTRL);
-       val &= ~BIT(0);
+       val &= ~PHY_TEST_PWR_DOWN;
        writel(val, pcie->parf + PARF_PHY_CTRL);
 
        ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
@@ -595,7 +603,7 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie)
        if (IS_ENABLED(CONFIG_PCI_MSI)) {
                u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
 
-               val |= BIT(31);
+               val |= EN;
                writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
        }
 
@@ -608,7 +616,7 @@ static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
 
        /* enable link training */
        val = readl(pcie->parf + PARF_LTSSM);
-       val |= BIT(8);
+       val |= LTSSM_EN;
        writel(val, pcie->parf + PARF_LTSSM);
 }
 
@@ -715,7 +723,7 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
 
        /* enable PCIe clocks and resets */
        val = readl(pcie->parf + PARF_PHY_CTRL);
-       val &= ~BIT(0);
+       val &= ~PHY_TEST_PWR_DOWN;
        writel(val, pcie->parf + PARF_PHY_CTRL);
 
        /* change DBI base address */
@@ -723,15 +731,15 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
 
        /* MAC PHY_POWERDOWN MUX DISABLE  */
        val = readl(pcie->parf + PARF_SYS_CTRL);
-       val &= ~BIT(29);
+       val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
        writel(val, pcie->parf + PARF_SYS_CTRL);
 
        val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
-       val |= BIT(4);
+       val |= BYPASS;
        writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
 
        val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
-       val |= BIT(31);
+       val |= EN;
        writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
 
        return 0;
@@ -994,7 +1002,7 @@ static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie)
 
        /* enable PCIe clocks and resets */
        val = readl(pcie->parf + PARF_PHY_CTRL);
-       val &= ~BIT(0);
+       val &= ~PHY_TEST_PWR_DOWN;
        writel(val, pcie->parf + PARF_PHY_CTRL);
 
        /* change DBI base address */
@@ -1002,15 +1010,15 @@ static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie)
 
        /* MAC PHY_POWERDOWN MUX DISABLE  */
        val = readl(pcie->parf + PARF_SYS_CTRL);
-       val &= ~BIT(29);
+       val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
        writel(val, pcie->parf + PARF_SYS_CTRL);
 
        val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
-       val |= BIT(4);
+       val |= BYPASS;
        writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
 
        val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
-       val |= BIT(31);
+       val |= EN;
        writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
 
        return 0;
@@ -1159,7 +1167,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
                pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3);
 
        val = readl(pcie->parf + PARF_PHY_CTRL);
-       val &= ~BIT(0);
+       val &= ~PHY_TEST_PWR_DOWN;
        writel(val, pcie->parf + PARF_PHY_CTRL);
 
        writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
@@ -1275,7 +1283,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
 
        /* enable PCIe clocks and resets */
        val = readl(pcie->parf + PARF_PHY_CTRL);
-       val &= ~BIT(0);
+       val &= ~PHY_TEST_PWR_DOWN;
        writel(val, pcie->parf + PARF_PHY_CTRL);
 
        /* change DBI base address */
@@ -1283,11 +1291,11 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
 
        /* MAC PHY_POWERDOWN MUX DISABLE  */
        val = readl(pcie->parf + PARF_SYS_CTRL);
-       val &= ~BIT(29);
+       val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
        writel(val, pcie->parf + PARF_SYS_CTRL);
 
        val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
-       val |= BIT(4);
+       val |= BYPASS;
        writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
 
        /* Enable L1 and L1SS */
@@ -1296,7 +1304,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
        writel(val, pcie->parf + PARF_PM_CTRL);
 
        val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
-       val |= BIT(31);
+       val |= EN;
        writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
 
        return 0;
@@ -1388,7 +1396,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
                pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
 
        val = readl(pcie->parf + PARF_PHY_CTRL);
-       val &= ~BIT(0);
+       val &= ~PHY_TEST_PWR_DOWN;
        writel(val, pcie->parf + PARF_PHY_CTRL);
 
        writel(0, pcie->parf + PARF_DBI_BASE_ADDR);