arm64: dts: exynos: Move pmu and timer nodes out of soc
authorKrzysztof Kozlowski <krzk@kernel.org>
Mon, 15 Apr 2019 18:34:39 +0000 (20:34 +0200)
committerKrzysztof Kozlowski <krzk@kernel.org>
Wed, 24 Apr 2019 17:57:15 +0000 (19:57 +0200)
The ARM PMU and ARM architected timer nodes are part of ARM CPU design
therefore they should not be inside the soc node.  This also fixes DTC
W=1 warnings like:

    arch/arm64/boot/dts/exynos/exynos7.dtsi:472.11-480.5:
        Warning (simple_bus_reg): /soc/arm-pmu: missing or empty reg/ranges property
    arch/arm64/boot/dts/exynos/exynos7.dtsi:482.9-492.5:
        Warning (simple_bus_reg): /soc/timer: missing or empty reg/ranges property

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
arch/arm64/boot/dts/exynos/exynos5433.dtsi
arch/arm64/boot/dts/exynos/exynos7.dtsi

index 41ecbc49c61eaa58a93fc1841e174855e2d86db8..62cedf9855cfdeabc54afcbeb2f8fefe9aa66980 100644 (file)
 
        interrupt-parent = <&gic>;
 
+       arm_a53_pmu {
+               compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+       };
+
+       arm_a57_pmu {
+               compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
+               interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
                #size-cells = <1>;
                ranges;
 
-               arm_a53_pmu {
-                       compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
-                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
-               };
-
-               arm_a57_pmu {
-                       compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
-                       interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
-               };
-
                chipid@10000000 {
                        compatible = "samsung,exynos4210-chipid";
                        reg = <0x10000000 0x100>;
index 967558a93d8204d5a55f7b5d4ce05c14863f5f97..f83ad4c491f29c256ae070b915e50eeff522629e 100644 (file)
                tmuctrl0 = &tmuctrl_0;
        };
 
+       arm-pmu {
+               compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
+               interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
+                                    <&cpu_atlas2>, <&cpu_atlas3>;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
                        status = "disabled";
                };
 
-               arm-pmu {
-                       compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
-                       interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-affinity = <&cpu_atlas0>, <&cpu_atlas1>,
-                                            <&cpu_atlas2>, <&cpu_atlas3>;
-               };
-
-               timer {
-                       compatible = "arm,armv8-timer";
-                       interrupts = <GIC_PPI 13
-                                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-                                    <GIC_PPI 14
-                                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-                                    <GIC_PPI 11
-                                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-                                    <GIC_PPI 10
-                                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
-               };
-
                pmu_system_controller: system-controller@105c0000 {
                        compatible = "samsung,exynos7-pmu", "syscon";
                        reg = <0x105c0000 0x5000>;
                        };
                };
        };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <GIC_PPI 13
+                               (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14
+                               (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11
+                               (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10
+                               (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+       };
 };
 
 #include "exynos7-pinctrl.dtsi"