ARM: dts: meson8: add the cortex-a9-pmu compatible PMU

Enable the performance monitor unit on Meson8.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index dcc9292d2ffaa055d388f0b6291752ad62bd5d5d..7b16ea61e914d13265372257afb0c0232af85439 100644 (file)
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -57,7 +57,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               cpu@200 {
+               cpu0: cpu@200 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        next-level-cache = <&L2>;
@@ -66,7 +66,7 @@
                        resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
                };
 
-               cpu@201 {
+               cpu1: cpu@201 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        next-level-cache = <&L2>;
@@ -75,7 +75,7 @@
                        resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
                };
 
-               cpu@202 {
+               cpu2: cpu@202 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        next-level-cache = <&L2>;
@@ -84,7 +84,7 @@
                        resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
                };
 
-               cpu@203 {
+               cpu3: cpu@203 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        next-level-cache = <&L2>;
@@ -94,6 +94,15 @@
                };
        };
 
+       pmu {
+               compatible = "arm,cortex-a9-pmu";
+               interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+       };
+
        reserved-memory {
                #address-cells = <1>;
                #size-cells = <1>;