PCI: layerscape: Add workaround for lost link capabilities during reset

The endpoint controller loses the Maximum Link Width and Supported Link Speed
value from the Link Capabilities Register - initially configured by the Reset
Configuration Word (RCW) - during a link-down or hot reset event.

Address this issue in the endpoint event handler.

Link: https://lore.kernel.org/r/20230720135834.1977616-2-Frank.Li@nxp.com
Fixes: a805770d8a22 ("PCI: layerscape: Add EP mode support")
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>

diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index e0969ff2ddf7717015e04e88881b8cfb71f823d2..b1faf41a2fae57c35da3095ca5bcb04ab32a3b65 100644 (file)
--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -45,6 +45,7 @@ struct ls_pcie_ep {
        struct pci_epc_features         *ls_epc;
        const struct ls_pcie_ep_drvdata *drvdata;
        int                             irq;
+       u32                             lnkcap;
        bool                            big_endian;
 };
 
@@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
        struct ls_pcie_ep *pcie = dev_id;
        struct dw_pcie *pci = pcie->pci;
        u32 val, cfg;
+       u8 offset;
 
        val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR);
        ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);
@@ -81,6 +83,19 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)
                return IRQ_NONE;
 
        if (val & PEX_PF0_PME_MES_DR_LUD) {
+
+               offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+
+               /*
+                * The values of the Maximum Link Width and Supported Link
+                * Speed from the Link Capabilities Register will be lost
+                * during link down or hot reset. Restore initial value
+                * that configured by the Reset Configuration Word (RCW).
+                */
+               dw_pcie_dbi_ro_wr_en(pci);
+               dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap);
+               dw_pcie_dbi_ro_wr_dis(pci);
+
                cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG);
                cfg |= PEX_PF0_CFG_READY;
                ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg);
@@ -216,6 +231,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
        struct ls_pcie_ep *pcie;
        struct pci_epc_features *ls_epc;
        struct resource *dbi_base;
+       u8 offset;
        int ret;
 
        pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
@@ -252,6 +268,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
 
        platform_set_drvdata(pdev, pcie);
 
+       offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+       pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
+
        ret = dw_pcie_ep_init(&pci->ep);
        if (ret)
                return ret;