PCI: dwc: Add EDMA_UNROLL capability flag
authorYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Wed, 18 Oct 2023 08:56:22 +0000 (17:56 +0900)
committerKrzysztof Wilczyński <kwilczynski@kernel.org>
Fri, 20 Oct 2023 12:12:56 +0000 (12:12 +0000)
Renesas R-Car Gen4 PCIe controllers have an unexpected register value in
the eDMA CTRL register.

So, add a new capability flag "EDMA_UNROLL" which would force the unrolled
eDMA mapping for the problematic device.

Suggested-by: Serge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/linux-pci/20231018085631.1121289-7-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
drivers/pci/controller/dwc/pcie-designware.c
drivers/pci/controller/dwc/pcie-designware.h

index 2b60d20dfdf59d52e892cfcfab3a022a4535779a..1f900be945565939e8618a8554ab24d0f51df933 100644 (file)
@@ -887,8 +887,14 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci)
         * Indirect eDMA CSRs access has been completely removed since v5.40a
         * thus no space is now reserved for the eDMA channels viewport and
         * former DMA CTRL register is no longer fixed to FFs.
+        *
+        * Note that Renesas R-Car S4-8's PCIe controllers for unknown reason
+        * have zeros in the eDMA CTRL register even though the HW-manual
+        * explicitly states there must FFs if the unrolled mapping is enabled.
+        * For such cases the low-level drivers are supposed to manually
+        * activate the unrolled mapping to bypass the auto-detection procedure.
         */
-       if (dw_pcie_ver_is_ge(pci, 540A))
+       if (dw_pcie_ver_is_ge(pci, 540A) || dw_pcie_cap_is(pci, EDMA_UNROLL))
                val = 0xFFFFFFFF;
        else
                val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
index 6189884b4eface549e919e91eaddf01ef104b44b..e10f7e18b13a4289f1b783460c033be7e3de33a9 100644 (file)
@@ -51,8 +51,9 @@
 
 /* DWC PCIe controller capabilities */
 #define DW_PCIE_CAP_REQ_RES            0
-#define DW_PCIE_CAP_IATU_UNROLL                1
-#define DW_PCIE_CAP_CDM_CHECK          2
+#define DW_PCIE_CAP_EDMA_UNROLL                1
+#define DW_PCIE_CAP_IATU_UNROLL                2
+#define DW_PCIE_CAP_CDM_CHECK          3
 
 #define dw_pcie_cap_is(_pci, _cap) \
        test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)