arm64: dts: qcom: sc7280: Add GENI I2C/SPI DMA channels
authorVinod Koul <vkoul@kernel.org>
Thu, 21 Apr 2022 11:55:25 +0000 (17:25 +0530)
committerBjorn Andersson <bjorn.andersson@linaro.org>
Sat, 23 Apr 2022 15:57:21 +0000 (10:57 -0500)
The GENI I2C and SPI controllers may use the GPI DMA engine, define the
rx and tx channels for these controllers to enable this.

Co-developed-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
Signed-off-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220421115526.1828659-2-vkoul@kernel.org
arch/arm64/boot/dts/qcom/sc7280.dtsi

index 43641db0e7deba4052be5dc21f0f0b0d68c4c33a..f72451f7f5395b562e42284d70f8de6c918cf700 100644 (file)
@@ -12,6 +12,7 @@
 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
+#include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/interconnect/qcom,sc7280.h>
                                                <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config",
                                                        "qup-memory";
+                               dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
                                                <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config",
                                                        "qup-memory";
+                               dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
                                                <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 1 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config",
                                                        "qup-memory";
+                               dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
                                                <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config",
                                                        "qup-memory";
+                               dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
                                                <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 3 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config",
                                                        "qup-memory";
+                               dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
                                                <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 4 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config",
                                                        "qup-memory";
+                               dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
                                                <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 5 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config",
                                                        "qup-memory";
+                               dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 6 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
                                                <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 6 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config",
                                                        "qup-memory";
+                               dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
+                                      <&gpi_dma0 1 7 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
                                                <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
+                                      <&gpi_dma0 1 7 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config",
                                                        "qup-memory";
+                               dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                                                <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config",
                                                        "qup-memory";
+                               dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                                                <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config",
                                                        "qup-memory";
+                               dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                                                <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 2 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config",
                                                        "qup-memory";
+                               dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                                                <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config",
                                                        "qup-memory";
+                               dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                                                <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config",
                                                        "qup-memory";
+                               dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 5 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                                                <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 5 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config",
                                                        "qup-memory";
+                               dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 6 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                                                <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 6 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                                <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
                                interconnect-names = "qup-core", "qup-config",
                                                        "qup-memory";
+                               dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
+                                      <&gpi_dma1 1 7 QCOM_GPI_I2C>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };
 
                                interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                                                <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
                                interconnect-names = "qup-core", "qup-config";
+                               dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
+                                      <&gpi_dma1 1 7 QCOM_GPI_SPI>;
+                               dma-names = "tx", "rx";
                                status = "disabled";
                        };