tcg: Remove TCG_TARGET_TLB_DISPLACEMENT_BITS
authorRichard Henderson <richard.henderson@linaro.org>
Tue, 28 Mar 2023 00:41:20 +0000 (17:41 -0700)
committerRichard Henderson <richard.henderson@linaro.org>
Tue, 30 May 2023 16:51:51 +0000 (09:51 -0700)
The last use was removed by e77c89fb086a.

Fixes: e77c89fb086a ("cputlb: Remove static tlb sizing")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
tcg/aarch64/tcg-target.h
tcg/arm/tcg-target.h
tcg/i386/tcg-target.h
tcg/mips/tcg-target.h
tcg/ppc/tcg-target.h
tcg/riscv/tcg-target.h
tcg/s390x/tcg-target.h
tcg/sparc64/tcg-target.h
tcg/tci/tcg-target.h

index 192a2758c595455c342e4d686e7bdec0e0d44470..ce64de06e573413ec97367a47ca333fbbe64ef6a 100644 (file)
@@ -16,7 +16,6 @@
 #include "host/cpuinfo.h"
 
 #define TCG_TARGET_INSN_UNIT_SIZE  4
-#define TCG_TARGET_TLB_DISPLACEMENT_BITS 24
 #define MAX_CODE_GEN_BUFFER_SIZE  ((size_t)-1)
 
 typedef enum {
index 65efc538f41e9907aa74e79d2c84c5ca725c23b6..c649db72a67e49f38c10dfe754283ffc1ccf7f7f 100644 (file)
@@ -31,7 +31,6 @@ extern int arm_arch;
 #define use_armv7_instructions  (__ARM_ARCH >= 7 || arm_arch >= 7)
 
 #define TCG_TARGET_INSN_UNIT_SIZE 4
-#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
 #define MAX_CODE_GEN_BUFFER_SIZE  UINT32_MAX
 
 typedef enum {
index b167f1e8d675e71e53ebb84ae9fb4dd6a882300d..1468f8ef25b6e79c4934af112a4c7ca83d20fbed 100644 (file)
@@ -28,7 +28,6 @@
 #include "host/cpuinfo.h"
 
 #define TCG_TARGET_INSN_UNIT_SIZE  1
-#define TCG_TARGET_TLB_DISPLACEMENT_BITS 31
 
 #ifdef __x86_64__
 # define TCG_TARGET_REG_BITS  64
index 8fbb6c6507e4302731a37bb2c6ceb0f414149dd9..e4806f6ff5dc6e3aa7adbe480fc3e7bd0c50f8f8 100644 (file)
@@ -36,7 +36,6 @@
 #endif
 
 #define TCG_TARGET_INSN_UNIT_SIZE 4
-#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
 #define TCG_TARGET_NB_REGS 32
 
 #define MAX_CODE_GEN_BUFFER_SIZE  ((size_t)-1)
index 204b70f86aa524f5c4d843991448a69476fe7f57..40f20b0c1a65d3f3f8e820746b8ab7973e03ae58 100644 (file)
@@ -34,7 +34,6 @@
 
 #define TCG_TARGET_NB_REGS 64
 #define TCG_TARGET_INSN_UNIT_SIZE 4
-#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
 
 typedef enum {
     TCG_REG_R0,  TCG_REG_R1,  TCG_REG_R2,  TCG_REG_R3,
index 62fe61af7b4f71ddbabecf24e380cfd88963ce35..54fdff0caa9e14228d148b2a03f4f97a21e5b7d0 100644 (file)
@@ -35,7 +35,6 @@
 #define TCG_TARGET_REG_BITS 64
 
 #define TCG_TARGET_INSN_UNIT_SIZE 4
-#define TCG_TARGET_TLB_DISPLACEMENT_BITS 20
 #define TCG_TARGET_NB_REGS 32
 #define MAX_CODE_GEN_BUFFER_SIZE  ((size_t)-1)
 
index ec969521721546fbc240c32c0aedeca269752016..9a405003b974f33b5b40ee16163d2cd8fdc6a403 100644 (file)
@@ -26,7 +26,6 @@
 #define S390_TCG_TARGET_H
 
 #define TCG_TARGET_INSN_UNIT_SIZE 2
-#define TCG_TARGET_TLB_DISPLACEMENT_BITS 19
 
 /* We have a +- 4GB range on the branches; leave some slop.  */
 #define MAX_CODE_GEN_BUFFER_SIZE  (3 * GiB)
index 31c5537379b6fd2cebab4b72250b7fc37041d92f..d454278811dc03abb2ad8f43ceae005e92a3a873 100644 (file)
@@ -26,7 +26,6 @@
 #define SPARC_TCG_TARGET_H
 
 #define TCG_TARGET_INSN_UNIT_SIZE 4
-#define TCG_TARGET_TLB_DISPLACEMENT_BITS 32
 #define TCG_TARGET_NB_REGS 32
 #define MAX_CODE_GEN_BUFFER_SIZE  (2 * GiB)
 
index 28dc6d5cfccac74c40b51cd69bca05e1cbc3fa50..60a6ed65ced9969e33d3173d2333c8ef7c0b6286 100644 (file)
@@ -42,7 +42,6 @@
 
 #define TCG_TARGET_INTERPRETER 1
 #define TCG_TARGET_INSN_UNIT_SIZE 4
-#define TCG_TARGET_TLB_DISPLACEMENT_BITS 32
 #define MAX_CODE_GEN_BUFFER_SIZE  ((size_t)-1)
 
 #if UINTPTR_MAX == UINT32_MAX