* recall us...
*/
DMA_hold_DREQ(fdctrl->dma_chann);
- DMA_schedule(fdctrl->dma_chann);
+ DMA_schedule();
} else {
/* Start transfer */
fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
}
static QEMUBH *dma_bh;
+static bool dma_bh_scheduled;
static void DMA_run (void)
{
running = 0;
out:
- if (rearm)
+ if (rearm) {
qemu_bh_schedule_idle(dma_bh);
+ dma_bh_scheduled = true;
+ }
}
static void DMA_run_bh(void *unused)
{
+ dma_bh_scheduled = false;
DMA_run();
}
return len;
}
-/* request the emulator to transfer a new DMA memory block ASAP */
-void DMA_schedule(int nchan)
+/* request the emulator to transfer a new DMA memory block ASAP (even
+ * if the idle bottom half would not have exited the iothread yet).
+ */
+void DMA_schedule(void)
{
- struct dma_cont *d = &dma_controllers[nchan > 3];
-
- qemu_irq_pulse(*d->cpu_request_exit);
+ if (dma_bh_scheduled) {
+ qemu_notify_event();
+ }
}
static void dma_reset(void *opaque)
}
void DMA_hold_DREQ (int nchan) {}
void DMA_release_DREQ (int nchan) {}
-void DMA_schedule(int nchan) {}
+void DMA_schedule(void) {}
void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
{
}
void DMA_hold_DREQ (int nchan) {}
void DMA_release_DREQ (int nchan) {}
-void DMA_schedule(int nchan) {}
+void DMA_schedule(void) {}
void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
{
int DMA_write_memory (int nchan, void *buf, int pos, int size);
void DMA_hold_DREQ (int nchan);
void DMA_release_DREQ (int nchan);
-void DMA_schedule(int nchan);
+void DMA_schedule(void);
void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit);
void DMA_register_channel (int nchan,
DMA_transfer_handler transfer_handler,