perf/x86/msr: Add Alder Lake CPU support

PPERF and SMI_COUNT MSRs are also supported on Alder Lake.

The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.

The patch has been tested on real hardware.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/1618237865-33448-24-git-send-email-kan.liang@linux.intel.com

diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 680404c58cb17b4bcbcdca90eaf6679b902904e2..c853b28efa334546a104c4dbb25c43a0665faa6f 100644 (file)
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -100,6 +100,8 @@ static bool test_intel(int idx, void *data)
        case INTEL_FAM6_TIGERLAKE_L:
        case INTEL_FAM6_TIGERLAKE:
        case INTEL_FAM6_ROCKETLAKE:
+       case INTEL_FAM6_ALDERLAKE:
+       case INTEL_FAM6_ALDERLAKE_L:
                if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
                        return true;
                break;