drm/amdgpu: Correct Transmit Margin masks

Previously we masked PCIe Link Control 2 register values with "7 << 9",
which was apparently intended to be the Transmit Margin field, but instead
was the high order bit of Transmit Margin, the Enter Modified Compliance
bit, and the Compliance SOS bit.

Correct the mask to "7 << 7", which is the Transmit Margin field.

Link: https://lore.kernel.org/r/20191112173503.176611-3-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index b81bb414fcb300a98312fa7d60c5ced4c72d05f7..13a5696d2a6a2a563bfa072500c4c1a2a407f4da 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1498,13 +1498,13 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
 
                                /* linkctl2 */
                                pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 9));
-                               tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+                               tmp16 &= ~((1 << 4) | (7 << 7));
+                               tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
                                pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
 
                                pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 9));
-                               tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+                               tmp16 &= ~((1 << 4) | (7 << 7));
+                               tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
                                pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
 
                                tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 493af42152f265cf7e4452b4db12bb7bb0b92725..1e350172dc7bbd7f9f62904a3856e73e4fd38b31 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1737,13 +1737,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
                                pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
 
                                pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 9));
-                               tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
+                               tmp16 &= ~((1 << 4) | (7 << 7));
+                               tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
                                pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
 
                                pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 9));
-                               tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
+                               tmp16 &= ~((1 << 4) | (7 << 7));
+                               tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
                                pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
 
                                tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);